328 lines
8.9 KiB
C
328 lines
8.9 KiB
C
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include "chan.h"
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#include "hdmi.h"
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#include "head.h"
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#include "ior.h"
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#include <nvif/class.h>
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void
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g84_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet,
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u8 rekey, u8 *avi, u8 avi_size, u8 *vendor, u8 vendor_size)
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{
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struct nvkm_device *device = ior->disp->engine.subdev.device;
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const u32 ctrl = 0x40000000 * enable |
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0x1f000000 /* ??? */ |
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max_ac_packet << 16 |
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rekey;
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const u32 hoff = head * 0x800;
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struct packed_hdmi_infoframe avi_infoframe;
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struct packed_hdmi_infoframe vendor_infoframe;
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pack_hdmi_infoframe(&avi_infoframe, avi, avi_size);
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pack_hdmi_infoframe(&vendor_infoframe, vendor, vendor_size);
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if (!(ctrl & 0x40000000)) {
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nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000);
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nvkm_mask(device, 0x61653c + hoff, 0x00000001, 0x00000000);
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nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);
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nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);
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return;
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}
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/* AVI InfoFrame */
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nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);
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if (avi_size) {
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nvkm_wr32(device, 0x616528 + hoff, avi_infoframe.header);
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nvkm_wr32(device, 0x61652c + hoff, avi_infoframe.subpack0_low);
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nvkm_wr32(device, 0x616530 + hoff, avi_infoframe.subpack0_high);
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nvkm_wr32(device, 0x616534 + hoff, avi_infoframe.subpack1_low);
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nvkm_wr32(device, 0x616538 + hoff, avi_infoframe.subpack1_high);
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nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001);
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}
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/* Audio InfoFrame */
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nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);
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nvkm_wr32(device, 0x616508 + hoff, 0x000a0184);
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nvkm_wr32(device, 0x61650c + hoff, 0x00000071);
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nvkm_wr32(device, 0x616510 + hoff, 0x00000000);
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nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001);
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/* Vendor InfoFrame */
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nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000);
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if (vendor_size) {
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nvkm_wr32(device, 0x616544 + hoff, vendor_infoframe.header);
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nvkm_wr32(device, 0x616548 + hoff, vendor_infoframe.subpack0_low);
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nvkm_wr32(device, 0x61654c + hoff, vendor_infoframe.subpack0_high);
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/* Is there a second (or up to fourth?) set of subpack registers here? */
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/* nvkm_wr32(device, 0x616550 + hoff, vendor_infoframe->subpack1_low); */
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/* nvkm_wr32(device, 0x616554 + hoff, vendor_infoframe->subpack1_high); */
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nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001);
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}
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nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
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nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
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nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
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/* ??? */
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nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
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nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
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nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
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/* HDMI_CTRL */
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nvkm_mask(device, 0x6165a4 + hoff, 0x5f1f007f, ctrl);
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}
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static const struct nvkm_ior_func
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g84_sor = {
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.state = nv50_sor_state,
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.power = nv50_sor_power,
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.clock = nv50_sor_clock,
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.hdmi = {
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.ctrl = g84_sor_hdmi_ctrl,
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},
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};
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int
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g84_sor_new(struct nvkm_disp *disp, int id)
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{
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return nvkm_ior_new_(&g84_sor, disp, SOR, id, false);
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}
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static const struct nvkm_disp_mthd_list
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g84_disp_ovly_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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{ 0x0080, 0x000000 },
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{ 0x0084, 0x6109a0 },
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{ 0x0088, 0x6109c0 },
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{ 0x008c, 0x6109c8 },
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{ 0x0090, 0x6109b4 },
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{ 0x0094, 0x610970 },
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{ 0x00a0, 0x610998 },
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{ 0x00a4, 0x610964 },
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{ 0x00c0, 0x610958 },
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{ 0x00e0, 0x6109a8 },
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{ 0x00e4, 0x6109d0 },
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{ 0x00e8, 0x6109d8 },
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{ 0x0100, 0x61094c },
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{ 0x0104, 0x610984 },
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{ 0x0108, 0x61098c },
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{ 0x0800, 0x6109f8 },
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{ 0x0808, 0x610a08 },
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{ 0x080c, 0x610a10 },
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{ 0x0810, 0x610a00 },
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{}
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}
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};
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static const struct nvkm_disp_chan_mthd
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g84_disp_ovly_mthd = {
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.name = "Overlay",
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.addr = 0x000540,
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.prev = 0x000004,
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.data = {
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{ "Global", 1, &g84_disp_ovly_mthd_base },
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{}
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}
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};
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const struct nvkm_disp_chan_user
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g84_disp_ovly = {
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.func = &nv50_disp_dmac_func,
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.ctrl = 3,
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.user = 3,
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.mthd = &g84_disp_ovly_mthd,
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};
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static const struct nvkm_disp_mthd_list
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g84_disp_base_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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{ 0x0080, 0x000000 },
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{ 0x0084, 0x0008c4 },
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{ 0x0088, 0x0008d0 },
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{ 0x008c, 0x0008dc },
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{ 0x0090, 0x0008e4 },
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{ 0x0094, 0x610884 },
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{ 0x00a0, 0x6108a0 },
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{ 0x00a4, 0x610878 },
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{ 0x00c0, 0x61086c },
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{ 0x00c4, 0x610800 },
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{ 0x00c8, 0x61080c },
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{ 0x00cc, 0x610818 },
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{ 0x00e0, 0x610858 },
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{ 0x00e4, 0x610860 },
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{ 0x00e8, 0x6108ac },
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{ 0x00ec, 0x6108b4 },
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{ 0x00fc, 0x610824 },
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{ 0x0100, 0x610894 },
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{ 0x0104, 0x61082c },
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{ 0x0110, 0x6108bc },
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{ 0x0114, 0x61088c },
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{}
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}
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};
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static const struct nvkm_disp_chan_mthd
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g84_disp_base_mthd = {
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.name = "Base",
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.addr = 0x000540,
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.prev = 0x000004,
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.data = {
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{ "Global", 1, &g84_disp_base_mthd_base },
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{ "Image", 2, &nv50_disp_base_mthd_image },
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{}
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}
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};
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const struct nvkm_disp_chan_user
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g84_disp_base = {
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.func = &nv50_disp_dmac_func,
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.ctrl = 1,
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.user = 1,
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.mthd = &g84_disp_base_mthd,
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};
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const struct nvkm_disp_mthd_list
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g84_disp_core_mthd_dac = {
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.mthd = 0x0080,
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.addr = 0x000008,
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.data = {
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{ 0x0400, 0x610b58 },
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{ 0x0404, 0x610bdc },
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{ 0x0420, 0x610bc4 },
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{}
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}
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};
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const struct nvkm_disp_mthd_list
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g84_disp_core_mthd_head = {
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.mthd = 0x0400,
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.addr = 0x000540,
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.data = {
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{ 0x0800, 0x610ad8 },
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{ 0x0804, 0x610ad0 },
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{ 0x0808, 0x610a48 },
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{ 0x080c, 0x610a78 },
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{ 0x0810, 0x610ac0 },
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{ 0x0814, 0x610af8 },
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{ 0x0818, 0x610b00 },
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{ 0x081c, 0x610ae8 },
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{ 0x0820, 0x610af0 },
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{ 0x0824, 0x610b08 },
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{ 0x0828, 0x610b10 },
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{ 0x082c, 0x610a68 },
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{ 0x0830, 0x610a60 },
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{ 0x0834, 0x000000 },
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{ 0x0838, 0x610a40 },
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{ 0x0840, 0x610a24 },
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{ 0x0844, 0x610a2c },
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{ 0x0848, 0x610aa8 },
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{ 0x084c, 0x610ab0 },
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{ 0x085c, 0x610c5c },
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{ 0x0860, 0x610a84 },
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{ 0x0864, 0x610a90 },
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{ 0x0868, 0x610b18 },
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{ 0x086c, 0x610b20 },
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{ 0x0870, 0x610ac8 },
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{ 0x0874, 0x610a38 },
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{ 0x0878, 0x610c50 },
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{ 0x0880, 0x610a58 },
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{ 0x0884, 0x610a9c },
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{ 0x089c, 0x610c68 },
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{ 0x08a0, 0x610a70 },
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{ 0x08a4, 0x610a50 },
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{ 0x08a8, 0x610ae0 },
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{ 0x08c0, 0x610b28 },
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{ 0x08c4, 0x610b30 },
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{ 0x08c8, 0x610b40 },
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{ 0x08d4, 0x610b38 },
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{ 0x08d8, 0x610b48 },
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{ 0x08dc, 0x610b50 },
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{ 0x0900, 0x610a18 },
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{ 0x0904, 0x610ab8 },
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{ 0x0910, 0x610c70 },
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{ 0x0914, 0x610c78 },
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{}
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}
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};
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const struct nvkm_disp_chan_mthd
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g84_disp_core_mthd = {
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.name = "Core",
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.addr = 0x000000,
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.prev = 0x000004,
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.data = {
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{ "Global", 1, &nv50_disp_core_mthd_base },
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{ "DAC", 3, &g84_disp_core_mthd_dac },
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{ "SOR", 2, &nv50_disp_core_mthd_sor },
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{ "PIOR", 3, &nv50_disp_core_mthd_pior },
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{ "HEAD", 2, &g84_disp_core_mthd_head },
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{}
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}
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};
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const struct nvkm_disp_chan_user
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g84_disp_core = {
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.func = &nv50_disp_core_func,
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.ctrl = 0,
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.user = 0,
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.mthd = &g84_disp_core_mthd,
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};
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static const struct nvkm_disp_func
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g84_disp = {
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.oneinit = nv50_disp_oneinit,
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.init = nv50_disp_init,
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.fini = nv50_disp_fini,
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.intr = nv50_disp_intr,
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.super = nv50_disp_super,
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.uevent = &nv50_disp_chan_uevent,
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.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
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.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
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.sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new },
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.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
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.root = { 0,0,G82_DISP },
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.user = {
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{{0,0,G82_DISP_CURSOR }, nvkm_disp_chan_new, &nv50_disp_curs },
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{{0,0,G82_DISP_OVERLAY }, nvkm_disp_chan_new, &nv50_disp_oimm },
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{{0,0,G82_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, & g84_disp_base },
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{{0,0,G82_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, & g84_disp_core },
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{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, & g84_disp_ovly },
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{}
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},
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};
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int
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g84_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_disp **pdisp)
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{
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return nvkm_disp_new_(&g84_disp, device, type, inst, pdisp);
|
||
|
|
}
|