75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright © 2018-2020 Intel Corporation
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*/
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#ifndef __KMB_PLANE_H__
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#define __KMB_PLANE_H__
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#include <drm/drm_fourcc.h>
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#include <drm/drm_plane.h>
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#define LCD_INT_VL0_ERR ((LAYER0_DMA_FIFO_UNDERFLOW) | \
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(LAYER0_DMA_FIFO_OVERFLOW) | \
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(LAYER0_DMA_CB_FIFO_OVERFLOW) | \
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(LAYER0_DMA_CB_FIFO_UNDERFLOW) | \
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(LAYER0_DMA_CR_FIFO_OVERFLOW) | \
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(LAYER0_DMA_CR_FIFO_UNDERFLOW))
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#define LCD_INT_VL1_ERR ((LAYER1_DMA_FIFO_UNDERFLOW) | \
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(LAYER1_DMA_FIFO_OVERFLOW) | \
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(LAYER1_DMA_CB_FIFO_OVERFLOW) | \
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(LAYER1_DMA_CB_FIFO_UNDERFLOW) | \
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(LAYER1_DMA_CR_FIFO_OVERFLOW) | \
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(LAYER1_DMA_CR_FIFO_UNDERFLOW))
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#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW)
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#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW)
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#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR)
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#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR)
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#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR)
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#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR)
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#define LCD_INT_DMA_ERR (LCD_INT_VL0_ERR | LCD_INT_VL1_ERR \
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| LCD_INT_GL0_ERR | LCD_INT_GL1_ERR)
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#define POSSIBLE_CRTCS 1
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#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane)
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#define POSSIBLE_CRTCS 1
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#define KMB_MAX_PLANES 2
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enum layer_id {
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LAYER_0,
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LAYER_1,
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LAYER_2,
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LAYER_3,
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/* KMB_MAX_PLANES */
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};
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enum sub_plane_id {
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Y_PLANE,
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U_PLANE,
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V_PLANE,
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MAX_SUB_PLANES,
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};
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struct kmb_plane {
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struct drm_plane base_plane;
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unsigned char id;
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};
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struct layer_status {
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bool disable;
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u32 ctrl;
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};
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struct disp_cfg {
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unsigned int width;
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unsigned int height;
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unsigned int format;
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};
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struct kmb_plane *kmb_plane_init(struct drm_device *drm);
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void kmb_plane_destroy(struct drm_plane *plane);
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#endif /* __KMB_PLANE_H__ */
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