104 lines
2.3 KiB
C
104 lines
2.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_div - mxs integer divider clock
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* @divider: the parent class
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* @ops: pointer to clk_ops of parent class
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* @reg: register address
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* @busy: busy bit shift
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*
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* The mxs divider clock is a subclass of basic clk_divider with an
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* addtional busy bit.
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*/
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struct clk_div {
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struct clk_divider divider;
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const struct clk_ops *ops;
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void __iomem *reg;
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u8 busy;
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};
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static inline struct clk_div *to_clk_div(struct clk_hw *hw)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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return container_of(divider, struct clk_div, divider);
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}
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static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_div *div = to_clk_div(hw);
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return div->ops->recalc_rate(&div->divider.hw, parent_rate);
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}
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static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_div *div = to_clk_div(hw);
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return div->ops->round_rate(&div->divider.hw, rate, prate);
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}
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static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_div *div = to_clk_div(hw);
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int ret;
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ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
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if (!ret)
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ret = mxs_clk_wait(div->reg, div->busy);
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return ret;
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}
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static const struct clk_ops clk_div_ops = {
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.recalc_rate = clk_div_recalc_rate,
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.round_rate = clk_div_round_rate,
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.set_rate = clk_div_set_rate,
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};
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struct clk *mxs_clk_div(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width, u8 busy)
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{
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struct clk_div *div;
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struct clk *clk;
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struct clk_init_data init;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_div_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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div->reg = reg;
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div->busy = busy;
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div->divider.reg = reg;
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div->divider.shift = shift;
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div->divider.width = width;
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div->divider.flags = CLK_DIVIDER_ONE_BASED;
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div->divider.lock = &mxs_lock;
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div->divider.hw.init = &init;
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div->ops = &clk_divider_ops;
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clk = clk_register(NULL, &div->divider.hw);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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