362 lines
10 KiB
C
362 lines
10 KiB
C
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/*****************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
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* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
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* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
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* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* (c) Copyright 2003-2008 Xilinx Inc.
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* All rights reserved.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*****************************************************************************/
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#include "buffer_icap.h"
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/* Indicates how many bytes will fit in a buffer. (1 BRAM) */
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#define XHI_MAX_BUFFER_BYTES 2048
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#define XHI_MAX_BUFFER_INTS (XHI_MAX_BUFFER_BYTES >> 2)
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/* File access and error constants */
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#define XHI_DEVICE_READ_ERROR -1
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#define XHI_DEVICE_WRITE_ERROR -2
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#define XHI_BUFFER_OVERFLOW_ERROR -3
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#define XHI_DEVICE_READ 0x1
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#define XHI_DEVICE_WRITE 0x0
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/* Constants for checking transfer status */
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#define XHI_CYCLE_DONE 0
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#define XHI_CYCLE_EXECUTING 1
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/* buffer_icap register offsets */
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/* Size of transfer, read & write */
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#define XHI_SIZE_REG_OFFSET 0x800L
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/* offset into bram, read & write */
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#define XHI_BRAM_OFFSET_REG_OFFSET 0x804L
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/* Read not Configure, direction of transfer. Write only */
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#define XHI_RNC_REG_OFFSET 0x808L
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/* Indicates transfer complete. Read only */
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#define XHI_STATUS_REG_OFFSET 0x80CL
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/* Constants for setting the RNC register */
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#define XHI_CONFIGURE 0x0UL
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#define XHI_READBACK 0x1UL
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/* Constants for the Done register */
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#define XHI_NOT_FINISHED 0x0UL
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#define XHI_FINISHED 0x1UL
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#define XHI_BUFFER_START 0
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/**
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* buffer_icap_get_status - Get the contents of the status register.
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* @drvdata: a pointer to the drvdata.
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*
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* The status register contains the ICAP status and the done bit.
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*
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* D8 - cfgerr
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* D7 - dalign
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* D6 - rip
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* D5 - in_abort_l
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* D4 - Always 1
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* D3 - Always 1
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* D2 - Always 1
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* D1 - Always 1
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* D0 - Done bit
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**/
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u32 buffer_icap_get_status(struct hwicap_drvdata *drvdata)
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{
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return in_be32(drvdata->base_address + XHI_STATUS_REG_OFFSET);
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}
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/**
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* buffer_icap_get_bram - Reads data from the storage buffer bram.
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* @base_address: contains the base address of the component.
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* @offset: The word offset from which the data should be read.
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*
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* A bram is used as a configuration memory cache. One frame of data can
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* be stored in this "storage buffer".
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**/
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static inline u32 buffer_icap_get_bram(void __iomem *base_address,
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u32 offset)
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{
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return in_be32(base_address + (offset << 2));
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}
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/**
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* buffer_icap_busy - Return true if the icap device is busy
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* @base_address: is the base address of the device
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*
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* The queries the low order bit of the status register, which
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* indicates whether the current configuration or readback operation
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* has completed.
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**/
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static inline bool buffer_icap_busy(void __iomem *base_address)
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{
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u32 status = in_be32(base_address + XHI_STATUS_REG_OFFSET);
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return (status & 1) == XHI_NOT_FINISHED;
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}
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/**
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* buffer_icap_set_size - Set the size register.
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* @base_address: is the base address of the device
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* @data: The size in bytes.
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*
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* The size register holds the number of 8 bit bytes to transfer between
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* bram and the icap (or icap to bram).
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**/
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static inline void buffer_icap_set_size(void __iomem *base_address,
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u32 data)
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{
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out_be32(base_address + XHI_SIZE_REG_OFFSET, data);
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}
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/**
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* buffer_icap_set_offset - Set the bram offset register.
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* @base_address: contains the base address of the device.
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* @data: is the value to be written to the data register.
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*
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* The bram offset register holds the starting bram address to transfer
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* data from during configuration or write data to during readback.
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**/
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static inline void buffer_icap_set_offset(void __iomem *base_address,
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u32 data)
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{
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out_be32(base_address + XHI_BRAM_OFFSET_REG_OFFSET, data);
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}
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/**
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* buffer_icap_set_rnc - Set the RNC (Readback not Configure) register.
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* @base_address: contains the base address of the device.
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* @data: is the value to be written to the data register.
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*
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* The RNC register determines the direction of the data transfer. It
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* controls whether a configuration or readback take place. Writing to
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* this register initiates the transfer. A value of 1 initiates a
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* readback while writing a value of 0 initiates a configuration.
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**/
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static inline void buffer_icap_set_rnc(void __iomem *base_address,
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u32 data)
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{
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out_be32(base_address + XHI_RNC_REG_OFFSET, data);
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}
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/**
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* buffer_icap_set_bram - Write data to the storage buffer bram.
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* @base_address: contains the base address of the component.
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* @offset: The word offset at which the data should be written.
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* @data: The value to be written to the bram offset.
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*
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* A bram is used as a configuration memory cache. One frame of data can
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* be stored in this "storage buffer".
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**/
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static inline void buffer_icap_set_bram(void __iomem *base_address,
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u32 offset, u32 data)
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{
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out_be32(base_address + (offset << 2), data);
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}
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/**
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* buffer_icap_device_read - Transfer bytes from ICAP to the storage buffer.
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* @drvdata: a pointer to the drvdata.
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* @offset: The storage buffer start address.
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* @count: The number of words (32 bit) to read from the
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* device (ICAP).
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**/
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static int buffer_icap_device_read(struct hwicap_drvdata *drvdata,
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u32 offset, u32 count)
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{
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s32 retries = 0;
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void __iomem *base_address = drvdata->base_address;
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if (buffer_icap_busy(base_address))
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return -EBUSY;
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if ((offset + count) > XHI_MAX_BUFFER_INTS)
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return -EINVAL;
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/* setSize count*4 to get bytes. */
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buffer_icap_set_size(base_address, (count << 2));
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buffer_icap_set_offset(base_address, offset);
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buffer_icap_set_rnc(base_address, XHI_READBACK);
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while (buffer_icap_busy(base_address)) {
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retries++;
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if (retries > XHI_MAX_RETRIES)
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return -EBUSY;
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}
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return 0;
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};
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/**
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* buffer_icap_device_write - Transfer bytes from ICAP to the storage buffer.
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* @drvdata: a pointer to the drvdata.
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* @offset: The storage buffer start address.
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* @count: The number of words (32 bit) to read from the
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* device (ICAP).
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**/
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static int buffer_icap_device_write(struct hwicap_drvdata *drvdata,
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u32 offset, u32 count)
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{
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s32 retries = 0;
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void __iomem *base_address = drvdata->base_address;
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if (buffer_icap_busy(base_address))
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return -EBUSY;
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if ((offset + count) > XHI_MAX_BUFFER_INTS)
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return -EINVAL;
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/* setSize count*4 to get bytes. */
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buffer_icap_set_size(base_address, count << 2);
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buffer_icap_set_offset(base_address, offset);
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buffer_icap_set_rnc(base_address, XHI_CONFIGURE);
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while (buffer_icap_busy(base_address)) {
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retries++;
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if (retries > XHI_MAX_RETRIES)
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return -EBUSY;
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}
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return 0;
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};
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/**
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* buffer_icap_reset - Reset the logic of the icap device.
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* @drvdata: a pointer to the drvdata.
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*
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* Writing to the status register resets the ICAP logic in an internal
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* version of the core. For the version of the core published in EDK,
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* this is a noop.
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**/
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void buffer_icap_reset(struct hwicap_drvdata *drvdata)
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{
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out_be32(drvdata->base_address + XHI_STATUS_REG_OFFSET, 0xFEFE);
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}
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/**
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* buffer_icap_set_configuration - Load a partial bitstream from system memory.
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* @drvdata: a pointer to the drvdata.
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* @data: Kernel address of the partial bitstream.
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* @size: the size of the partial bitstream in 32 bit words.
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**/
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int buffer_icap_set_configuration(struct hwicap_drvdata *drvdata, u32 *data,
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u32 size)
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{
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int status;
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s32 buffer_count = 0;
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bool dirty = false;
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u32 i;
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void __iomem *base_address = drvdata->base_address;
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/* Loop through all the data */
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for (i = 0, buffer_count = 0; i < size; i++) {
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/* Copy data to bram */
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buffer_icap_set_bram(base_address, buffer_count, data[i]);
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dirty = true;
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if (buffer_count < XHI_MAX_BUFFER_INTS - 1) {
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buffer_count++;
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continue;
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}
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/* Write data to ICAP */
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status = buffer_icap_device_write(
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drvdata,
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XHI_BUFFER_START,
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XHI_MAX_BUFFER_INTS);
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if (status != 0) {
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/* abort. */
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buffer_icap_reset(drvdata);
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return status;
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}
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buffer_count = 0;
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dirty = false;
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}
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/* Write unwritten data to ICAP */
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if (dirty) {
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/* Write data to ICAP */
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status = buffer_icap_device_write(drvdata, XHI_BUFFER_START,
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buffer_count);
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if (status != 0) {
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/* abort. */
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buffer_icap_reset(drvdata);
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}
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return status;
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}
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return 0;
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};
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/**
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* buffer_icap_get_configuration - Read configuration data from the device.
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* @drvdata: a pointer to the drvdata.
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* @data: Address of the data representing the partial bitstream
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* @size: the size of the partial bitstream in 32 bit words.
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**/
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int buffer_icap_get_configuration(struct hwicap_drvdata *drvdata, u32 *data,
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u32 size)
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{
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int status;
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s32 buffer_count = 0;
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u32 i;
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void __iomem *base_address = drvdata->base_address;
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/* Loop through all the data */
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for (i = 0, buffer_count = XHI_MAX_BUFFER_INTS; i < size; i++) {
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if (buffer_count == XHI_MAX_BUFFER_INTS) {
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u32 words_remaining = size - i;
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u32 words_to_read =
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words_remaining <
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XHI_MAX_BUFFER_INTS ? words_remaining :
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XHI_MAX_BUFFER_INTS;
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/* Read data from ICAP */
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status = buffer_icap_device_read(
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drvdata,
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XHI_BUFFER_START,
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words_to_read);
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if (status != 0) {
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/* abort. */
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buffer_icap_reset(drvdata);
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return status;
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}
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buffer_count = 0;
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}
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/* Copy data from bram */
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data[i] = buffer_icap_get_bram(base_address, buffer_count);
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buffer_count++;
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}
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return 0;
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};
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