382 lines
11 KiB
C
382 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* OPAL hypervisor Maintenance interrupt handling support in PowerNV.
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*
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* Copyright 2014 IBM Corporation
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* Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <asm/opal.h>
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#include <asm/cputable.h>
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#include <asm/machdep.h>
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#include "powernv.h"
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static int opal_hmi_handler_nb_init;
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struct OpalHmiEvtNode {
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struct list_head list;
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struct OpalHMIEvent hmi_evt;
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};
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struct xstop_reason {
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uint32_t xstop_reason;
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const char *unit_failed;
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const char *description;
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};
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static LIST_HEAD(opal_hmi_evt_list);
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static DEFINE_SPINLOCK(opal_hmi_evt_lock);
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static void print_core_checkstop_reason(const char *level,
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struct OpalHMIEvent *hmi_evt)
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{
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int i;
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static const struct xstop_reason xstop_reason[] = {
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{ CORE_CHECKSTOP_IFU_REGFILE, "IFU",
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"RegFile core check stop" },
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{ CORE_CHECKSTOP_IFU_LOGIC, "IFU", "Logic core check stop" },
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{ CORE_CHECKSTOP_PC_DURING_RECOV, "PC",
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"Core checkstop during recovery" },
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{ CORE_CHECKSTOP_ISU_REGFILE, "ISU",
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"RegFile core check stop (mapper error)" },
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{ CORE_CHECKSTOP_ISU_LOGIC, "ISU", "Logic core check stop" },
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{ CORE_CHECKSTOP_FXU_LOGIC, "FXU", "Logic core check stop" },
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{ CORE_CHECKSTOP_VSU_LOGIC, "VSU", "Logic core check stop" },
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{ CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE, "PC",
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"Recovery in maintenance mode" },
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{ CORE_CHECKSTOP_LSU_REGFILE, "LSU",
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"RegFile core check stop" },
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{ CORE_CHECKSTOP_PC_FWD_PROGRESS, "PC",
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"Forward Progress Error" },
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{ CORE_CHECKSTOP_LSU_LOGIC, "LSU", "Logic core check stop" },
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{ CORE_CHECKSTOP_PC_LOGIC, "PC", "Logic core check stop" },
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{ CORE_CHECKSTOP_PC_HYP_RESOURCE, "PC",
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"Hypervisor Resource error - core check stop" },
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{ CORE_CHECKSTOP_PC_HANG_RECOV_FAILED, "PC",
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"Hang Recovery Failed (core check stop)" },
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{ CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED, "PC",
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"Ambiguous Hang Detected (unknown source)" },
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{ CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ, "PC",
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"Debug Trigger Error inject" },
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{ CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ, "PC",
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"Hypervisor check stop via SPRC/SPRD" },
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};
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/* Validity check */
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if (!hmi_evt->u.xstop_error.xstop_reason) {
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printk("%s Unknown Core check stop.\n", level);
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return;
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}
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printk("%s CPU PIR: %08x\n", level,
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be32_to_cpu(hmi_evt->u.xstop_error.u.pir));
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for (i = 0; i < ARRAY_SIZE(xstop_reason); i++)
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if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) &
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xstop_reason[i].xstop_reason)
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printk("%s [Unit: %-3s] %s\n", level,
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xstop_reason[i].unit_failed,
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xstop_reason[i].description);
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}
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static void print_nx_checkstop_reason(const char *level,
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struct OpalHMIEvent *hmi_evt)
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{
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int i;
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static const struct xstop_reason xstop_reason[] = {
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{ NX_CHECKSTOP_SHM_INVAL_STATE_ERR, "DMA & Engine",
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"SHM invalid state error" },
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{ NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1, "DMA & Engine",
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"DMA invalid state error bit 15" },
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{ NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2, "DMA & Engine",
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"DMA invalid state error bit 16" },
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{ NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 0 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 1 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 2 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 3 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 4 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 5 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 6 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 7 invalid state error" },
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{ NX_CHECKSTOP_DMA_CRB_UE, "DMA & Engine",
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"UE error on CRB(CSB address, CCB)" },
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{ NX_CHECKSTOP_DMA_CRB_SUE, "DMA & Engine",
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"SUE error on CRB(CSB address, CCB)" },
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{ NX_CHECKSTOP_PBI_ISN_UE, "PowerBus Interface",
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"CRB Kill ISN received while holding ISN with UE error" },
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};
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/* Validity check */
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if (!hmi_evt->u.xstop_error.xstop_reason) {
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printk("%s Unknown NX check stop.\n", level);
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return;
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}
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printk("%s NX checkstop on CHIP ID: %x\n", level,
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be32_to_cpu(hmi_evt->u.xstop_error.u.chip_id));
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for (i = 0; i < ARRAY_SIZE(xstop_reason); i++)
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if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) &
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xstop_reason[i].xstop_reason)
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printk("%s [Unit: %-3s] %s\n", level,
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xstop_reason[i].unit_failed,
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xstop_reason[i].description);
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}
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static void print_npu_checkstop_reason(const char *level,
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struct OpalHMIEvent *hmi_evt)
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{
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uint8_t reason, reason_count, i;
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/*
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* We may not have a checkstop reason on some combination of
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* hardware and/or skiboot version
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*/
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if (!hmi_evt->u.xstop_error.xstop_reason) {
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printk("%s NPU checkstop on chip %x\n", level,
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be32_to_cpu(hmi_evt->u.xstop_error.u.chip_id));
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return;
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}
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/*
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* NPU2 has 3 FIRs. Reason encoded on a byte as:
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* 2 bits for the FIR number
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* 6 bits for the bit number
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* It may be possible to find several reasons.
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*
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* We don't display a specific message per FIR bit as there
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* are too many and most are meaningless without the workbook
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* and/or hw team help anyway.
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*/
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reason_count = sizeof(hmi_evt->u.xstop_error.xstop_reason) /
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sizeof(reason);
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for (i = 0; i < reason_count; i++) {
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reason = (hmi_evt->u.xstop_error.xstop_reason >> (8 * i)) & 0xFF;
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if (reason)
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printk("%s NPU checkstop on chip %x: FIR%d bit %d is set\n",
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level,
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be32_to_cpu(hmi_evt->u.xstop_error.u.chip_id),
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reason >> 6, reason & 0x3F);
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}
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}
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static void print_checkstop_reason(const char *level,
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struct OpalHMIEvent *hmi_evt)
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{
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uint8_t type = hmi_evt->u.xstop_error.xstop_type;
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switch (type) {
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case CHECKSTOP_TYPE_CORE:
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print_core_checkstop_reason(level, hmi_evt);
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break;
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case CHECKSTOP_TYPE_NX:
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print_nx_checkstop_reason(level, hmi_evt);
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break;
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case CHECKSTOP_TYPE_NPU:
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print_npu_checkstop_reason(level, hmi_evt);
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break;
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default:
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printk("%s Unknown Malfunction Alert of type %d\n",
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level, type);
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break;
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}
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}
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static void print_hmi_event_info(struct OpalHMIEvent *hmi_evt)
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{
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const char *level, *sevstr, *error_info;
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static const char *hmi_error_types[] = {
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"Malfunction Alert",
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"Processor Recovery done",
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"Processor recovery occurred again",
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"Processor recovery occurred for masked error",
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"Timer facility experienced an error",
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"TFMR SPR is corrupted",
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"UPS (Uninterrupted Power System) Overflow indication",
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"An XSCOM operation failure",
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"An XSCOM operation completed",
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"SCOM has set a reserved FIR bit to cause recovery",
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"Debug trigger has set a reserved FIR bit to cause recovery",
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"A hypervisor resource error occurred",
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"CAPP recovery process is in progress",
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};
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static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
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DEFAULT_RATELIMIT_BURST);
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/* Print things out */
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if (hmi_evt->version < OpalHMIEvt_V1) {
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pr_err("HMI Interrupt, Unknown event version %d !\n",
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hmi_evt->version);
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return;
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}
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switch (hmi_evt->severity) {
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case OpalHMI_SEV_NO_ERROR:
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level = KERN_INFO;
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sevstr = "Harmless";
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break;
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case OpalHMI_SEV_WARNING:
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level = KERN_WARNING;
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sevstr = "";
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break;
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case OpalHMI_SEV_ERROR_SYNC:
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level = KERN_ERR;
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sevstr = "Severe";
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break;
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case OpalHMI_SEV_FATAL:
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default:
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level = KERN_ERR;
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sevstr = "Fatal";
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break;
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}
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if (hmi_evt->severity != OpalHMI_SEV_NO_ERROR || __ratelimit(&rs)) {
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printk("%s%s Hypervisor Maintenance interrupt [%s]\n",
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level, sevstr,
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hmi_evt->disposition == OpalHMI_DISPOSITION_RECOVERED ?
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"Recovered" : "Not recovered");
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error_info = hmi_evt->type < ARRAY_SIZE(hmi_error_types) ?
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hmi_error_types[hmi_evt->type]
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: "Unknown";
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printk("%s Error detail: %s\n", level, error_info);
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printk("%s HMER: %016llx\n", level,
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be64_to_cpu(hmi_evt->hmer));
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if ((hmi_evt->type == OpalHMI_ERROR_TFAC) ||
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(hmi_evt->type == OpalHMI_ERROR_TFMR_PARITY))
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printk("%s TFMR: %016llx\n", level,
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be64_to_cpu(hmi_evt->tfmr));
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}
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if (hmi_evt->version < OpalHMIEvt_V2)
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return;
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/* OpalHMIEvt_V2 and above provides reason for malfunction alert. */
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if (hmi_evt->type == OpalHMI_ERROR_MALFUNC_ALERT)
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print_checkstop_reason(level, hmi_evt);
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}
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static void hmi_event_handler(struct work_struct *work)
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{
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unsigned long flags;
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struct OpalHMIEvent *hmi_evt;
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struct OpalHmiEvtNode *msg_node;
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uint8_t disposition;
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struct opal_msg msg;
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int unrecoverable = 0;
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spin_lock_irqsave(&opal_hmi_evt_lock, flags);
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while (!list_empty(&opal_hmi_evt_list)) {
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msg_node = list_entry(opal_hmi_evt_list.next,
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struct OpalHmiEvtNode, list);
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list_del(&msg_node->list);
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spin_unlock_irqrestore(&opal_hmi_evt_lock, flags);
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hmi_evt = (struct OpalHMIEvent *) &msg_node->hmi_evt;
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print_hmi_event_info(hmi_evt);
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disposition = hmi_evt->disposition;
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kfree(msg_node);
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/*
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* Check if HMI event has been recovered or not. If not
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* then kernel can't continue, we need to panic.
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* But before we do that, display all the HMI event
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* available on the list and set unrecoverable flag to 1.
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*/
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if (disposition != OpalHMI_DISPOSITION_RECOVERED)
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unrecoverable = 1;
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spin_lock_irqsave(&opal_hmi_evt_lock, flags);
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}
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spin_unlock_irqrestore(&opal_hmi_evt_lock, flags);
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if (unrecoverable) {
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/* Pull all HMI events from OPAL before we panic. */
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while (opal_get_msg(__pa(&msg), sizeof(msg)) == OPAL_SUCCESS) {
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u32 type;
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type = be32_to_cpu(msg.msg_type);
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/* skip if not HMI event */
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if (type != OPAL_MSG_HMI_EVT)
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continue;
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/* HMI event info starts from param[0] */
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hmi_evt = (struct OpalHMIEvent *)&msg.params[0];
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print_hmi_event_info(hmi_evt);
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}
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pnv_platform_error_reboot(NULL, "Unrecoverable HMI exception");
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}
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}
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static DECLARE_WORK(hmi_event_work, hmi_event_handler);
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/*
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* opal_handle_hmi_event - notifier handler that queues up HMI events
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* to be preocessed later.
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*/
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static int opal_handle_hmi_event(struct notifier_block *nb,
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unsigned long msg_type, void *msg)
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{
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unsigned long flags;
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struct OpalHMIEvent *hmi_evt;
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struct opal_msg *hmi_msg = msg;
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struct OpalHmiEvtNode *msg_node;
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/* Sanity Checks */
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if (msg_type != OPAL_MSG_HMI_EVT)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
/* HMI event info starts from param[0] */
|
||
|
|
hmi_evt = (struct OpalHMIEvent *)&hmi_msg->params[0];
|
||
|
|
|
||
|
|
/* Delay the logging of HMI events to workqueue. */
|
||
|
|
msg_node = kzalloc(sizeof(*msg_node), GFP_ATOMIC);
|
||
|
|
if (!msg_node) {
|
||
|
|
pr_err("HMI: out of memory, Opal message event not handled\n");
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
memcpy(&msg_node->hmi_evt, hmi_evt, sizeof(*hmi_evt));
|
||
|
|
|
||
|
|
spin_lock_irqsave(&opal_hmi_evt_lock, flags);
|
||
|
|
list_add(&msg_node->list, &opal_hmi_evt_list);
|
||
|
|
spin_unlock_irqrestore(&opal_hmi_evt_lock, flags);
|
||
|
|
|
||
|
|
schedule_work(&hmi_event_work);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct notifier_block opal_hmi_handler_nb = {
|
||
|
|
.notifier_call = opal_handle_hmi_event,
|
||
|
|
.next = NULL,
|
||
|
|
.priority = 0,
|
||
|
|
};
|
||
|
|
|
||
|
|
int __init opal_hmi_handler_init(void)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (!opal_hmi_handler_nb_init) {
|
||
|
|
ret = opal_message_notifier_register(
|
||
|
|
OPAL_MSG_HMI_EVT, &opal_hmi_handler_nb);
|
||
|
|
if (ret) {
|
||
|
|
pr_err("%s: Can't register OPAL event notifier (%d)\n",
|
||
|
|
__func__, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
opal_hmi_handler_nb_init = 1;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|