95 lines
3.4 KiB
C
95 lines
3.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Cell Broadband Engine Performance Monitor
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*
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* (C) Copyright IBM Corporation 2006
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*
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* Author:
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* David Erb (djerb@us.ibm.com)
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* Kevin Corry (kevcorry@us.ibm.com)
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*/
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#ifndef __ASM_CELL_PMU_H__
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#define __ASM_CELL_PMU_H__
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/* The Cell PMU has four hardware performance counters, which can be
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* configured as four 32-bit counters or eight 16-bit counters.
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*/
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#define NR_PHYS_CTRS 4
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#define NR_CTRS (NR_PHYS_CTRS * 2)
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/* Macros for the pm_control register. */
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#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
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#define CBE_PM_ENABLE_PERF_MON 0x80000000
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#define CBE_PM_STOP_AT_MAX 0x40000000
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#define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)
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#define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)
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#define CBE_PM_TRACE_BUF_OVFLW(bit) (((bit) & 0x1) << 17)
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#define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)
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#define CBE_PM_FREEZE_ALL_CTRS 0x00100000
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#define CBE_PM_ENABLE_EXT_TRACE 0x00008000
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#define CBE_PM_SPU_ADDR_TRACE_SET(msk) (((msk) & 0x3) << 9)
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/* Macros for the trace_address register. */
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#define CBE_PM_TRACE_BUF_FULL 0x00000800
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#define CBE_PM_TRACE_BUF_EMPTY 0x00000400
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#define CBE_PM_TRACE_BUF_DATA_COUNT(ta) ((ta) & 0x3ff)
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#define CBE_PM_TRACE_BUF_MAX_COUNT 0x400
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/* Macros for the pm07_control registers. */
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#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
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#define CBE_PM_CTR_INPUT_CONTROL 0x02000000
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#define CBE_PM_CTR_POLARITY 0x01000000
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#define CBE_PM_CTR_COUNT_CYCLES 0x00800000
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#define CBE_PM_CTR_ENABLE 0x00400000
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#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)
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#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)
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#define PM07_CTR_POLARITY(x) (((x) & 1) << 24)
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#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)
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#define PM07_CTR_ENABLE(x) (((x) & 1) << 22)
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/* Macros for the pm_status register. */
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#define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
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enum pm_reg_name {
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group_control,
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debug_bus_control,
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trace_address,
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ext_tr_timer,
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pm_status,
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pm_control,
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pm_interval,
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pm_start_stop,
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};
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/* Routines for reading/writing the PMU registers. */
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extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
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extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
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extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
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extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
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extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
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extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
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extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
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extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
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extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
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extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
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extern void cbe_enable_pm(u32 cpu);
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extern void cbe_disable_pm(u32 cpu);
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extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
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extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
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extern void cbe_disable_pm_interrupts(u32 cpu);
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extern u32 cbe_get_and_clear_pm_interrupts(u32 cpu);
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extern void cbe_sync_irq(int node);
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#define CBE_COUNT_SUPERVISOR_MODE 0
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#define CBE_COUNT_HYPERVISOR_MODE 1
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#define CBE_COUNT_PROBLEM_MODE 2
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#define CBE_COUNT_ALL_MODES 3
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#endif /* __ASM_CELL_PMU_H__ */
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