340 lines
10 KiB
C
340 lines
10 KiB
C
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/**
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*
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* Interface to the hardware Input Packet Data unit.
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*/
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#ifndef __CVMX_IPD_H__
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#define __CVMX_IPD_H__
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#include <asm/octeon/octeon-feature.h>
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#include <asm/octeon/cvmx-ipd-defs.h>
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#include <asm/octeon/cvmx-pip-defs.h>
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enum cvmx_ipd_mode {
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CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
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CVMX_IPD_OPC_MODE_STF = 1LL, /* All blocks into L2 */
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CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */
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CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */
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};
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#ifndef CVMX_ENABLE_LEN_M8_FIX
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#define CVMX_ENABLE_LEN_M8_FIX 0
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#endif
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/* CSR typedefs have been moved to cvmx-csr-*.h */
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typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t;
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typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t;
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typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
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typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
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/**
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* Configure IPD
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*
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* @mbuff_size: Packets buffer size in 8 byte words
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* @first_mbuff_skip:
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* Number of 8 byte words to skip in the first buffer
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* @not_first_mbuff_skip:
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* Number of 8 byte words to skip in each following buffer
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* @first_back: Must be same as first_mbuff_skip / 128
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* @second_back:
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* Must be same as not_first_mbuff_skip / 128
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* @wqe_fpa_pool:
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* FPA pool to get work entries from
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* @cache_mode:
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* @back_pres_enable_flag:
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* Enable or disable port back pressure
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*/
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static inline void cvmx_ipd_config(uint64_t mbuff_size,
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uint64_t first_mbuff_skip,
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uint64_t not_first_mbuff_skip,
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uint64_t first_back,
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uint64_t second_back,
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uint64_t wqe_fpa_pool,
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enum cvmx_ipd_mode cache_mode,
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uint64_t back_pres_enable_flag)
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{
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cvmx_ipd_mbuff_first_skip_t first_skip;
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cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
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union cvmx_ipd_packet_mbuff_size size;
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cvmx_ipd_first_next_ptr_back_t first_back_struct;
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cvmx_ipd_second_next_ptr_back_t second_back_struct;
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union cvmx_ipd_wqe_fpa_queue wqe_pool;
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union cvmx_ipd_ctl_status ipd_ctl_reg;
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first_skip.u64 = 0;
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first_skip.s.skip_sz = first_mbuff_skip;
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cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
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not_first_skip.u64 = 0;
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not_first_skip.s.skip_sz = not_first_mbuff_skip;
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cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
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size.u64 = 0;
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size.s.mb_size = mbuff_size;
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cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
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first_back_struct.u64 = 0;
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first_back_struct.s.back = first_back;
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cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
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second_back_struct.u64 = 0;
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second_back_struct.s.back = second_back;
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cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64);
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wqe_pool.u64 = 0;
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wqe_pool.s.wqe_pool = wqe_fpa_pool;
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cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
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ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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ipd_ctl_reg.s.opc_mode = cache_mode;
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ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
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cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
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/* Note: the example RED code that used to be here has been moved to
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cvmx_helper_setup_red */
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}
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/**
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* Enable IPD
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*/
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static inline void cvmx_ipd_enable(void)
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{
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union cvmx_ipd_ctl_status ipd_reg;
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ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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if (ipd_reg.s.ipd_en) {
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cvmx_dprintf
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("Warning: Enabling IPD when IPD already enabled.\n");
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}
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ipd_reg.s.ipd_en = 1;
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#if CVMX_ENABLE_LEN_M8_FIX
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if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
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ipd_reg.s.len_m8 = TRUE;
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#endif
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cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
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}
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/**
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* Disable IPD
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*/
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static inline void cvmx_ipd_disable(void)
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{
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union cvmx_ipd_ctl_status ipd_reg;
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ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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ipd_reg.s.ipd_en = 0;
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cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
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}
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/**
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* Supportive function for cvmx_fpa_shutdown_pool.
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*/
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static inline void cvmx_ipd_free_ptr(void)
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{
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/* Only CN38XXp{1,2} cannot read pointer out of the IPD */
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if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)
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&& !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
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int no_wptr = 0;
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union cvmx_ipd_ptr_count ipd_ptr_count;
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ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
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/* Handle Work Queue Entry in cn56xx and cn52xx */
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if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
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union cvmx_ipd_ctl_status ipd_ctl_status;
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ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
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if (ipd_ctl_status.s.no_wptr)
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no_wptr = 1;
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}
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/* Free the prefetched WQE */
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if (ipd_ptr_count.s.wqev_cnt) {
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union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid;
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ipd_wqe_ptr_valid.u64 =
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cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
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if (no_wptr)
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cvmx_fpa_free(cvmx_phys_to_ptr
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((uint64_t) ipd_wqe_ptr_valid.s.
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ptr << 7), CVMX_FPA_PACKET_POOL,
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0);
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else
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cvmx_fpa_free(cvmx_phys_to_ptr
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((uint64_t) ipd_wqe_ptr_valid.s.
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ptr << 7), CVMX_FPA_WQE_POOL, 0);
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}
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/* Free all WQE in the fifo */
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if (ipd_ptr_count.s.wqe_pcnt) {
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int i;
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union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
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ipd_pwp_ptr_fifo_ctl.u64 =
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cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
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for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
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ipd_pwp_ptr_fifo_ctl.s.cena = 0;
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ipd_pwp_ptr_fifo_ctl.s.raddr =
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ipd_pwp_ptr_fifo_ctl.s.max_cnts +
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(ipd_pwp_ptr_fifo_ctl.s.wraddr +
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i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
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cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
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ipd_pwp_ptr_fifo_ctl.u64);
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ipd_pwp_ptr_fifo_ctl.u64 =
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cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
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if (no_wptr)
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cvmx_fpa_free(cvmx_phys_to_ptr
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((uint64_t)
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ipd_pwp_ptr_fifo_ctl.s.
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ptr << 7),
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CVMX_FPA_PACKET_POOL, 0);
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else
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cvmx_fpa_free(cvmx_phys_to_ptr
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((uint64_t)
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ipd_pwp_ptr_fifo_ctl.s.
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ptr << 7),
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CVMX_FPA_WQE_POOL, 0);
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}
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ipd_pwp_ptr_fifo_ctl.s.cena = 1;
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cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
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ipd_pwp_ptr_fifo_ctl.u64);
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}
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/* Free the prefetched packet */
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if (ipd_ptr_count.s.pktv_cnt) {
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union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid;
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ipd_pkt_ptr_valid.u64 =
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cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
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cvmx_fpa_free(cvmx_phys_to_ptr
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(ipd_pkt_ptr_valid.s.ptr << 7),
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CVMX_FPA_PACKET_POOL, 0);
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}
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/* Free the per port prefetched packets */
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if (1) {
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int i;
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union cvmx_ipd_prc_port_ptr_fifo_ctl
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ipd_prc_port_ptr_fifo_ctl;
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ipd_prc_port_ptr_fifo_ctl.u64 =
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cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
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for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
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i++) {
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ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
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ipd_prc_port_ptr_fifo_ctl.s.raddr =
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i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
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cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
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ipd_prc_port_ptr_fifo_ctl.u64);
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ipd_prc_port_ptr_fifo_ctl.u64 =
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cvmx_read_csr
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(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
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cvmx_fpa_free(cvmx_phys_to_ptr
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((uint64_t)
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ipd_prc_port_ptr_fifo_ctl.s.
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ptr << 7), CVMX_FPA_PACKET_POOL,
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0);
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}
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ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
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cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
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ipd_prc_port_ptr_fifo_ctl.u64);
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}
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/* Free all packets in the holding fifo */
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if (ipd_ptr_count.s.pfif_cnt) {
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int i;
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union cvmx_ipd_prc_hold_ptr_fifo_ctl
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ipd_prc_hold_ptr_fifo_ctl;
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ipd_prc_hold_ptr_fifo_ctl.u64 =
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cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
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for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
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ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
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ipd_prc_hold_ptr_fifo_ctl.s.raddr =
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(ipd_prc_hold_ptr_fifo_ctl.s.praddr +
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i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
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cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
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ipd_prc_hold_ptr_fifo_ctl.u64);
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ipd_prc_hold_ptr_fifo_ctl.u64 =
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cvmx_read_csr
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(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
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cvmx_fpa_free(cvmx_phys_to_ptr
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((uint64_t)
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ipd_prc_hold_ptr_fifo_ctl.s.
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ptr << 7), CVMX_FPA_PACKET_POOL,
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0);
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}
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ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
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cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
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ipd_prc_hold_ptr_fifo_ctl.u64);
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}
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/* Free all packets in the fifo */
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if (ipd_ptr_count.s.pkt_pcnt) {
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int i;
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union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
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ipd_pwp_ptr_fifo_ctl.u64 =
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cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
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for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
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ipd_pwp_ptr_fifo_ctl.s.cena = 0;
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ipd_pwp_ptr_fifo_ctl.s.raddr =
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(ipd_pwp_ptr_fifo_ctl.s.praddr +
|
||
|
|
i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
|
||
|
|
cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
|
||
|
|
ipd_pwp_ptr_fifo_ctl.u64);
|
||
|
|
ipd_pwp_ptr_fifo_ctl.u64 =
|
||
|
|
cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
|
||
|
|
cvmx_fpa_free(cvmx_phys_to_ptr
|
||
|
|
((uint64_t) ipd_pwp_ptr_fifo_ctl.
|
||
|
|
s.ptr << 7),
|
||
|
|
CVMX_FPA_PACKET_POOL, 0);
|
||
|
|
}
|
||
|
|
ipd_pwp_ptr_fifo_ctl.s.cena = 1;
|
||
|
|
cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
|
||
|
|
ipd_pwp_ptr_fifo_ctl.u64);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Reset the IPD to get all buffers out of it */
|
||
|
|
{
|
||
|
|
union cvmx_ipd_ctl_status ipd_ctl_status;
|
||
|
|
ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
|
||
|
|
ipd_ctl_status.s.reset = 1;
|
||
|
|
cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Reset the PIP */
|
||
|
|
{
|
||
|
|
union cvmx_pip_sft_rst pip_sft_rst;
|
||
|
|
pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
|
||
|
|
pip_sft_rst.s.rst = 1;
|
||
|
|
cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __CVMX_IPD_H__ */
|