549 lines
8.4 KiB
Plaintext
549 lines
8.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Condor board with R-Car V3H
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018 Cogent Embedded, Inc.
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &scif0;
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ethernet0 = &gether;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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d1_8v: regulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "D1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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d3_3v: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "D3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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hdmi-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con: endpoint {
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remote-endpoint = <&adv7511_out>;
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};
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};
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};
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lvds-decoder {
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compatible = "thine,thc63lvd1024";
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vcc-supply = <&d3_3v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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thc63lvd1024_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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port@2 {
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reg = <2>;
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thc63lvd1024_out: endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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};
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0 0x48000000 0 0x78000000>;
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};
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vddq_vin01: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "VDDQ_VIN01";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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x1_clk: x1-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <148500000>;
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};
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};
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&canfd {
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pinctrl-0 = <&canfd0_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel0 {
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status = "okay";
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};
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};
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&csi40 {
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status = "okay";
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ports {
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port@0 {
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csi40_in: endpoint {
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clock-lanes = <0>;
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data-lanes = <1 2 3 4>;
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remote-endpoint = <&max9286_out0>;
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};
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};
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};
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};
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&csi41 {
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status = "okay";
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ports {
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port@0 {
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csi41_in: endpoint {
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clock-lanes = <0>;
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data-lanes = <1 2 3 4>;
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remote-endpoint = <&max9286_out1>;
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};
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};
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};
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};
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&du {
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clocks = <&cpg CPG_MOD 724>,
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<&x1_clk>;
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clock-names = "du.0", "dclkin.0";
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status = "okay";
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&gether {
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pinctrl-0 = <&gether_pins>;
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pinctrl-names = "default";
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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renesas,no-ether-link;
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status = "okay";
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio4>;
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interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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io_expander0: gpio@20 {
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compatible = "onnn,pca9654";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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io_expander1: gpio@21 {
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compatible = "onnn,pca9654";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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hdmi@39 {
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compatible = "adi,adv7511w";
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reg = <0x39>;
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interrupt-parent = <&gpio1>;
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interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
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avdd-supply = <&d1_8v>;
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dvdd-supply = <&d1_8v>;
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pvdd-supply = <&d1_8v>;
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bgvdd-supply = <&d1_8v>;
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dvdd-3v-supply = <&d3_3v>;
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adi,input-depth = <8>;
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adi,input-colorspace = "rgb";
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adi,input-clock = "1x";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7511_in: endpoint {
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remote-endpoint = <&thc63lvd1024_out>;
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};
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};
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port@1 {
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reg = <1>;
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adv7511_out: endpoint {
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remote-endpoint = <&hdmi_con>;
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};
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};
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};
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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gmsl0: gmsl-deserializer@48 {
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compatible = "maxim,max9286";
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reg = <0x48>;
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maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
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enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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};
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port@2 {
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reg = <2>;
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};
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port@3 {
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reg = <3>;
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};
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port@4 {
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reg = <4>;
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max9286_out0: endpoint {
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clock-lanes = <0>;
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data-lanes = <1 2 3 4>;
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remote-endpoint = <&csi40_in>;
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};
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};
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};
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i2c-mux {
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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status = "disabled";
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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status = "disabled";
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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status = "disabled";
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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status = "disabled";
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};
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};
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};
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gmsl1: gmsl-deserializer@4a {
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compatible = "maxim,max9286";
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reg = <0x4a>;
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maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
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enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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};
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port@2 {
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reg = <2>;
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};
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port@3 {
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reg = <3>;
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};
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port@4 {
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reg = <4>;
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max9286_out1: endpoint {
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clock-lanes = <0>;
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data-lanes = <1 2 3 4>;
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remote-endpoint = <&csi41_in>;
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};
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};
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};
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i2c-mux {
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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status = "disabled";
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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status = "disabled";
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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status = "disabled";
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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status = "disabled";
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};
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};
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};
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};
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&lvds0 {
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status = "okay";
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ports {
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port@1 {
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lvds0_out: endpoint {
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remote-endpoint = <&thc63lvd1024_in>;
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};
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};
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};
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};
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&mmc0 {
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pinctrl-0 = <&mmc_pins>;
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pinctrl-1 = <&mmc_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&d3_3v>;
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vqmmc-supply = <&vddq_vin01>;
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mmc-hs200-1_8v;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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};
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&pciec {
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status = "okay";
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};
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&pcie_bus_clk {
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clock-frequency = <100000000>;
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};
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&pcie_phy {
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status = "okay";
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};
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&pfc {
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canfd0_pins: canfd0 {
|
||
|
|
groups = "canfd0_data_a";
|
||
|
|
function = "canfd0";
|
||
|
|
};
|
||
|
|
|
||
|
|
gether_pins: gether {
|
||
|
|
groups = "gether_mdio_a", "gether_rgmii",
|
||
|
|
"gether_txcrefclk", "gether_txcrefclk_mega";
|
||
|
|
function = "gether";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c0_pins: i2c0 {
|
||
|
|
groups = "i2c0";
|
||
|
|
function = "i2c0";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1_pins: i2c1 {
|
||
|
|
groups = "i2c1";
|
||
|
|
function = "i2c1";
|
||
|
|
};
|
||
|
|
|
||
|
|
mmc_pins: mmc {
|
||
|
|
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
|
||
|
|
function = "mmc";
|
||
|
|
power-source = <1800>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qspi0_pins: qspi0 {
|
||
|
|
groups = "qspi0_ctrl", "qspi0_data4";
|
||
|
|
function = "qspi0";
|
||
|
|
};
|
||
|
|
|
||
|
|
scif0_pins: scif0 {
|
||
|
|
groups = "scif0_data";
|
||
|
|
function = "scif0";
|
||
|
|
};
|
||
|
|
|
||
|
|
scif_clk_pins: scif_clk {
|
||
|
|
groups = "scif_clk_b";
|
||
|
|
function = "scif_clk";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&rpc {
|
||
|
|
pinctrl-0 = <&qspi0_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
flash@0 {
|
||
|
|
compatible = "spansion,s25fs512s", "jedec,spi-nor";
|
||
|
|
reg = <0>;
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
spi-rx-bus-width = <4>;
|
||
|
|
|
||
|
|
partitions {
|
||
|
|
compatible = "fixed-partitions";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
bootparam@0 {
|
||
|
|
reg = <0x00000000 0x040000>;
|
||
|
|
read-only;
|
||
|
|
};
|
||
|
|
cr7@40000 {
|
||
|
|
reg = <0x00040000 0x080000>;
|
||
|
|
read-only;
|
||
|
|
};
|
||
|
|
cert_header_sa3@c0000 {
|
||
|
|
reg = <0x000c0000 0x080000>;
|
||
|
|
read-only;
|
||
|
|
};
|
||
|
|
bl2@140000 {
|
||
|
|
reg = <0x00140000 0x040000>;
|
||
|
|
read-only;
|
||
|
|
};
|
||
|
|
cert_header_sa6@180000 {
|
||
|
|
reg = <0x00180000 0x040000>;
|
||
|
|
read-only;
|
||
|
|
};
|
||
|
|
bl31@1c0000 {
|
||
|
|
reg = <0x001c0000 0x460000>;
|
||
|
|
read-only;
|
||
|
|
};
|
||
|
|
uboot@640000 {
|
||
|
|
reg = <0x00640000 0x0c0000>;
|
||
|
|
read-only;
|
||
|
|
};
|
||
|
|
uboot-env@700000 {
|
||
|
|
reg = <0x00700000 0x040000>;
|
||
|
|
read-only;
|
||
|
|
};
|
||
|
|
dtb@740000 {
|
||
|
|
reg = <0x00740000 0x080000>;
|
||
|
|
};
|
||
|
|
kernel@7c0000 {
|
||
|
|
reg = <0x007c0000 0x1400000>;
|
||
|
|
};
|
||
|
|
user@1bc0000 {
|
||
|
|
reg = <0x01bc0000 0x2440000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&rwdt {
|
||
|
|
timeout-sec = <60>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&scif0 {
|
||
|
|
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&scif_clk {
|
||
|
|
clock-frequency = <14745600>;
|
||
|
|
};
|