1709 lines
50 KiB
Plaintext
1709 lines
50 KiB
Plaintext
|
// SPDX-License-Identifier: GPL-2.0
|
||
|
|
#include <dt-bindings/input/input.h>
|
||
|
|
|
||
|
|
/ {
|
||
|
|
model = "NVIDIA Tegra210 P2597 I/O board";
|
||
|
|
compatible = "nvidia,p2597", "nvidia,tegra210";
|
||
|
|
|
||
|
|
aliases {
|
||
|
|
ethernet = "/usb@70090000/ethernet@1";
|
||
|
|
};
|
||
|
|
|
||
|
|
host1x@50000000 {
|
||
|
|
dpaux@54040000 {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
vi@54080000 {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
avdd-dsi-csi-supply = <&vdd_dsi_csi>;
|
||
|
|
|
||
|
|
csi@838 {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sor@54580000 {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
avdd-io-hdmi-dp-supply = <&avdd_1v05>;
|
||
|
|
vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
|
||
|
|
hdmi-supply = <&vdd_hdmi>;
|
||
|
|
|
||
|
|
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
||
|
|
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
|
||
|
|
GPIO_ACTIVE_LOW>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pinmux: pinmux@700008d4 {
|
||
|
|
pinctrl-names = "boot";
|
||
|
|
pinctrl-0 = <&state_boot>;
|
||
|
|
|
||
|
|
state_boot: pinmux {
|
||
|
|
pex_l0_rst_n_pa0 {
|
||
|
|
nvidia,pins = "pex_l0_rst_n_pa0";
|
||
|
|
nvidia,function = "pe0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
pex_l0_clkreq_n_pa1 {
|
||
|
|
nvidia,pins = "pex_l0_clkreq_n_pa1";
|
||
|
|
nvidia,function = "pe0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
pex_wake_n_pa2 {
|
||
|
|
nvidia,pins = "pex_wake_n_pa2";
|
||
|
|
nvidia,function = "pe";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
pex_l1_rst_n_pa3 {
|
||
|
|
nvidia,pins = "pex_l1_rst_n_pa3";
|
||
|
|
nvidia,function = "pe1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
pex_l1_clkreq_n_pa4 {
|
||
|
|
nvidia,pins = "pex_l1_clkreq_n_pa4";
|
||
|
|
nvidia,function = "pe1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
sata_led_active_pa5 {
|
||
|
|
nvidia,pins = "sata_led_active_pa5";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pa6 {
|
||
|
|
nvidia,pins = "pa6";
|
||
|
|
nvidia,function = "sata";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap1_fs_pb0 {
|
||
|
|
nvidia,pins = "dap1_fs_pb0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap1_din_pb1 {
|
||
|
|
nvidia,pins = "dap1_din_pb1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap1_dout_pb2 {
|
||
|
|
nvidia,pins = "dap1_dout_pb2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap1_sclk_pb3 {
|
||
|
|
nvidia,pins = "dap1_sclk_pb3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi2_mosi_pb4 {
|
||
|
|
nvidia,pins = "spi2_mosi_pb4";
|
||
|
|
nvidia,function = "spi2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi2_miso_pb5 {
|
||
|
|
nvidia,pins = "spi2_miso_pb5";
|
||
|
|
nvidia,function = "spi2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi2_sck_pb6 {
|
||
|
|
nvidia,pins = "spi2_sck_pb6";
|
||
|
|
nvidia,function = "spi2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi2_cs0_pb7 {
|
||
|
|
nvidia,pins = "spi2_cs0_pb7";
|
||
|
|
nvidia,function = "spi2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi1_mosi_pc0 {
|
||
|
|
nvidia,pins = "spi1_mosi_pc0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi1_miso_pc1 {
|
||
|
|
nvidia,pins = "spi1_miso_pc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi1_sck_pc2 {
|
||
|
|
nvidia,pins = "spi1_sck_pc2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi1_cs0_pc3 {
|
||
|
|
nvidia,pins = "spi1_cs0_pc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi1_cs1_pc4 {
|
||
|
|
nvidia,pins = "spi1_cs1_pc4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi4_sck_pc5 {
|
||
|
|
nvidia,pins = "spi4_sck_pc5";
|
||
|
|
nvidia,function = "spi4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi4_cs0_pc6 {
|
||
|
|
nvidia,pins = "spi4_cs0_pc6";
|
||
|
|
nvidia,function = "spi4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi4_mosi_pc7 {
|
||
|
|
nvidia,pins = "spi4_mosi_pc7";
|
||
|
|
nvidia,function = "spi4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi4_miso_pd0 {
|
||
|
|
nvidia,pins = "spi4_miso_pd0";
|
||
|
|
nvidia,function = "spi4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart3_tx_pd1 {
|
||
|
|
nvidia,pins = "uart3_tx_pd1";
|
||
|
|
nvidia,function = "uartc";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart3_rx_pd2 {
|
||
|
|
nvidia,pins = "uart3_rx_pd2";
|
||
|
|
nvidia,function = "uartc";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart3_rts_pd3 {
|
||
|
|
nvidia,pins = "uart3_rts_pd3";
|
||
|
|
nvidia,function = "uartc";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart3_cts_pd4 {
|
||
|
|
nvidia,pins = "uart3_cts_pd4";
|
||
|
|
nvidia,function = "uartc";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dmic1_clk_pe0 {
|
||
|
|
nvidia,pins = "dmic1_clk_pe0";
|
||
|
|
nvidia,function = "i2s3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dmic1_dat_pe1 {
|
||
|
|
nvidia,pins = "dmic1_dat_pe1";
|
||
|
|
nvidia,function = "i2s3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dmic2_clk_pe2 {
|
||
|
|
nvidia,pins = "dmic2_clk_pe2";
|
||
|
|
nvidia,function = "i2s3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dmic2_dat_pe3 {
|
||
|
|
nvidia,pins = "dmic2_dat_pe3";
|
||
|
|
nvidia,function = "i2s3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dmic3_clk_pe4 {
|
||
|
|
nvidia,pins = "dmic3_clk_pe4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dmic3_dat_pe5 {
|
||
|
|
nvidia,pins = "dmic3_dat_pe5";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pe6 {
|
||
|
|
nvidia,pins = "pe6";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pe7 {
|
||
|
|
nvidia,pins = "pe7";
|
||
|
|
nvidia,function = "pwm3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen3_i2c_scl_pf0 {
|
||
|
|
nvidia,pins = "gen3_i2c_scl_pf0";
|
||
|
|
nvidia,function = "i2c3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen3_i2c_sda_pf1 {
|
||
|
|
nvidia,pins = "gen3_i2c_sda_pf1";
|
||
|
|
nvidia,function = "i2c3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart2_tx_pg0 {
|
||
|
|
nvidia,pins = "uart2_tx_pg0";
|
||
|
|
nvidia,function = "uartb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart2_rx_pg1 {
|
||
|
|
nvidia,pins = "uart2_rx_pg1";
|
||
|
|
nvidia,function = "uartb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart2_rts_pg2 {
|
||
|
|
nvidia,pins = "uart2_rts_pg2";
|
||
|
|
nvidia,function = "uartb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart2_cts_pg3 {
|
||
|
|
nvidia,pins = "uart2_cts_pg3";
|
||
|
|
nvidia,function = "uartb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
wifi_en_ph0 {
|
||
|
|
nvidia,pins = "wifi_en_ph0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
wifi_rst_ph1 {
|
||
|
|
nvidia,pins = "wifi_rst_ph1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
wifi_wake_ap_ph2 {
|
||
|
|
nvidia,pins = "wifi_wake_ap_ph2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
ap_wake_bt_ph3 {
|
||
|
|
nvidia,pins = "ap_wake_bt_ph3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
bt_rst_ph4 {
|
||
|
|
nvidia,pins = "bt_rst_ph4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
bt_wake_ap_ph5 {
|
||
|
|
nvidia,pins = "bt_wake_ap_ph5";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
ph6 {
|
||
|
|
nvidia,pins = "ph6";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
ap_wake_nfc_ph7 {
|
||
|
|
nvidia,pins = "ap_wake_nfc_ph7";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
nfc_en_pi0 {
|
||
|
|
nvidia,pins = "nfc_en_pi0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
nfc_int_pi1 {
|
||
|
|
nvidia,pins = "nfc_int_pi1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gps_en_pi2 {
|
||
|
|
nvidia,pins = "gps_en_pi2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gps_rst_pi3 {
|
||
|
|
nvidia,pins = "gps_rst_pi3";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart4_tx_pi4 {
|
||
|
|
nvidia,pins = "uart4_tx_pi4";
|
||
|
|
nvidia,function = "uartd";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart4_rx_pi5 {
|
||
|
|
nvidia,pins = "uart4_rx_pi5";
|
||
|
|
nvidia,function = "uartd";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart4_rts_pi6 {
|
||
|
|
nvidia,pins = "uart4_rts_pi6";
|
||
|
|
nvidia,function = "uartd";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart4_cts_pi7 {
|
||
|
|
nvidia,pins = "uart4_cts_pi7";
|
||
|
|
nvidia,function = "uartd";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen1_i2c_sda_pj0 {
|
||
|
|
nvidia,pins = "gen1_i2c_sda_pj0";
|
||
|
|
nvidia,function = "i2c1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen1_i2c_scl_pj1 {
|
||
|
|
nvidia,pins = "gen1_i2c_scl_pj1";
|
||
|
|
nvidia,function = "i2c1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gen2_i2c_scl_pj2 {
|
||
|
|
nvidia,pins = "gen2_i2c_scl_pj2";
|
||
|
|
nvidia,function = "i2c2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
gen2_i2c_sda_pj3 {
|
||
|
|
nvidia,pins = "gen2_i2c_sda_pj3";
|
||
|
|
nvidia,function = "i2c2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
dap4_fs_pj4 {
|
||
|
|
nvidia,pins = "dap4_fs_pj4";
|
||
|
|
nvidia,function = "i2s4b";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap4_din_pj5 {
|
||
|
|
nvidia,pins = "dap4_din_pj5";
|
||
|
|
nvidia,function = "i2s4b";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap4_dout_pj6 {
|
||
|
|
nvidia,pins = "dap4_dout_pj6";
|
||
|
|
nvidia,function = "i2s4b";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap4_sclk_pj7 {
|
||
|
|
nvidia,pins = "dap4_sclk_pj7";
|
||
|
|
nvidia,function = "i2s4b";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk0 {
|
||
|
|
nvidia,pins = "pk0";
|
||
|
|
nvidia,function = "i2s5b";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk1 {
|
||
|
|
nvidia,pins = "pk1";
|
||
|
|
nvidia,function = "i2s5b";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk2 {
|
||
|
|
nvidia,pins = "pk2";
|
||
|
|
nvidia,function = "i2s5b";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk3 {
|
||
|
|
nvidia,pins = "pk3";
|
||
|
|
nvidia,function = "i2s5b";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk4 {
|
||
|
|
nvidia,pins = "pk4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk5 {
|
||
|
|
nvidia,pins = "pk5";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk6 {
|
||
|
|
nvidia,pins = "pk6";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pk7 {
|
||
|
|
nvidia,pins = "pk7";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pl0 {
|
||
|
|
nvidia,pins = "pl0";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pl1 {
|
||
|
|
nvidia,pins = "pl1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_clk_pm0 {
|
||
|
|
nvidia,pins = "sdmmc1_clk_pm0";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_cmd_pm1 {
|
||
|
|
nvidia,pins = "sdmmc1_cmd_pm1";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_dat3_pm2 {
|
||
|
|
nvidia,pins = "sdmmc1_dat3_pm2";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_dat2_pm3 {
|
||
|
|
nvidia,pins = "sdmmc1_dat2_pm3";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_dat1_pm4 {
|
||
|
|
nvidia,pins = "sdmmc1_dat1_pm4";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc1_dat0_pm5 {
|
||
|
|
nvidia,pins = "sdmmc1_dat0_pm5";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_clk_pp0 {
|
||
|
|
nvidia,pins = "sdmmc3_clk_pp0";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_cmd_pp1 {
|
||
|
|
nvidia,pins = "sdmmc3_cmd_pp1";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_dat3_pp2 {
|
||
|
|
nvidia,pins = "sdmmc3_dat3_pp2";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_dat2_pp3 {
|
||
|
|
nvidia,pins = "sdmmc3_dat2_pp3";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_dat1_pp4 {
|
||
|
|
nvidia,pins = "sdmmc3_dat1_pp4";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
sdmmc3_dat0_pp5 {
|
||
|
|
nvidia,pins = "sdmmc3_dat0_pp5";
|
||
|
|
nvidia,function = "sdmmc3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam1_mclk_ps0 {
|
||
|
|
nvidia,pins = "cam1_mclk_ps0";
|
||
|
|
nvidia,function = "extperiph3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam2_mclk_ps1 {
|
||
|
|
nvidia,pins = "cam2_mclk_ps1";
|
||
|
|
nvidia,function = "extperiph3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_i2c_scl_ps2 {
|
||
|
|
nvidia,pins = "cam_i2c_scl_ps2";
|
||
|
|
nvidia,function = "i2cvi";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_i2c_sda_ps3 {
|
||
|
|
nvidia,pins = "cam_i2c_sda_ps3";
|
||
|
|
nvidia,function = "i2cvi";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_rst_ps4 {
|
||
|
|
nvidia,pins = "cam_rst_ps4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_af_en_ps5 {
|
||
|
|
nvidia,pins = "cam_af_en_ps5";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam_flash_en_ps6 {
|
||
|
|
nvidia,pins = "cam_flash_en_ps6";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam1_pwdn_ps7 {
|
||
|
|
nvidia,pins = "cam1_pwdn_ps7";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam2_pwdn_pt0 {
|
||
|
|
nvidia,pins = "cam2_pwdn_pt0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cam1_strobe_pt1 {
|
||
|
|
nvidia,pins = "cam1_strobe_pt1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart1_tx_pu0 {
|
||
|
|
nvidia,pins = "uart1_tx_pu0";
|
||
|
|
nvidia,function = "uarta";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart1_rx_pu1 {
|
||
|
|
nvidia,pins = "uart1_rx_pu1";
|
||
|
|
nvidia,function = "uarta";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart1_rts_pu2 {
|
||
|
|
nvidia,pins = "uart1_rts_pu2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
uart1_cts_pu3 {
|
||
|
|
nvidia,pins = "uart1_cts_pu3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_bl_pwm_pv0 {
|
||
|
|
nvidia,pins = "lcd_bl_pwm_pv0";
|
||
|
|
nvidia,function = "pwm0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_bl_en_pv1 {
|
||
|
|
nvidia,pins = "lcd_bl_en_pv1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_rst_pv2 {
|
||
|
|
nvidia,pins = "lcd_rst_pv2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_gpio1_pv3 {
|
||
|
|
nvidia,pins = "lcd_gpio1_pv3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_gpio2_pv4 {
|
||
|
|
nvidia,pins = "lcd_gpio2_pv4";
|
||
|
|
nvidia,function = "pwm1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
ap_ready_pv5 {
|
||
|
|
nvidia,pins = "ap_ready_pv5";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
touch_rst_pv6 {
|
||
|
|
nvidia,pins = "touch_rst_pv6";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
touch_clk_pv7 {
|
||
|
|
nvidia,pins = "touch_clk_pv7";
|
||
|
|
nvidia,function = "touch";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
modem_wake_ap_px0 {
|
||
|
|
nvidia,pins = "modem_wake_ap_px0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
touch_int_px1 {
|
||
|
|
nvidia,pins = "touch_int_px1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
motion_int_px2 {
|
||
|
|
nvidia,pins = "motion_int_px2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
als_prox_int_px3 {
|
||
|
|
nvidia,pins = "als_prox_int_px3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
temp_alert_px4 {
|
||
|
|
nvidia,pins = "temp_alert_px4";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_power_on_px5 {
|
||
|
|
nvidia,pins = "button_power_on_px5";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_vol_up_px6 {
|
||
|
|
nvidia,pins = "button_vol_up_px6";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_vol_down_px7 {
|
||
|
|
nvidia,pins = "button_vol_down_px7";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_slide_sw_py0 {
|
||
|
|
nvidia,pins = "button_slide_sw_py0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
button_home_py1 {
|
||
|
|
nvidia,pins = "button_home_py1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
lcd_te_py2 {
|
||
|
|
nvidia,pins = "lcd_te_py2";
|
||
|
|
nvidia,function = "displaya";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pwr_i2c_scl_py3 {
|
||
|
|
nvidia,pins = "pwr_i2c_scl_py3";
|
||
|
|
nvidia,function = "i2cpmu";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pwr_i2c_sda_py4 {
|
||
|
|
nvidia,pins = "pwr_i2c_sda_py4";
|
||
|
|
nvidia,function = "i2cpmu";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
clk_32k_out_py5 {
|
||
|
|
nvidia,pins = "clk_32k_out_py5";
|
||
|
|
nvidia,function = "soc";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz0 {
|
||
|
|
nvidia,pins = "pz0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz1 {
|
||
|
|
nvidia,pins = "pz1";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz2 {
|
||
|
|
nvidia,pins = "pz2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz3 {
|
||
|
|
nvidia,pins = "pz3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz4 {
|
||
|
|
nvidia,pins = "pz4";
|
||
|
|
nvidia,function = "sdmmc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pz5 {
|
||
|
|
nvidia,pins = "pz5";
|
||
|
|
nvidia,function = "soc";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap2_fs_paa0 {
|
||
|
|
nvidia,pins = "dap2_fs_paa0";
|
||
|
|
nvidia,function = "i2s2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap2_sclk_paa1 {
|
||
|
|
nvidia,pins = "dap2_sclk_paa1";
|
||
|
|
nvidia,function = "i2s2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap2_din_paa2 {
|
||
|
|
nvidia,pins = "dap2_din_paa2";
|
||
|
|
nvidia,function = "i2s2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dap2_dout_paa3 {
|
||
|
|
nvidia,pins = "dap2_dout_paa3";
|
||
|
|
nvidia,function = "i2s2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
aud_mclk_pbb0 {
|
||
|
|
nvidia,pins = "aud_mclk_pbb0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dvfs_pwm_pbb1 {
|
||
|
|
nvidia,pins = "dvfs_pwm_pbb1";
|
||
|
|
nvidia,function = "cldvfs";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
dvfs_clk_pbb2 {
|
||
|
|
nvidia,pins = "dvfs_clk_pbb2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gpio_x1_aud_pbb3 {
|
||
|
|
nvidia,pins = "gpio_x1_aud_pbb3";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
gpio_x3_aud_pbb4 {
|
||
|
|
nvidia,pins = "gpio_x3_aud_pbb4";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
hdmi_cec_pcc0 {
|
||
|
|
nvidia,pins = "hdmi_cec_pcc0";
|
||
|
|
nvidia,function = "cec";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
hdmi_int_dp_hpd_pcc1 {
|
||
|
|
nvidia,pins = "hdmi_int_dp_hpd_pcc1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spdif_out_pcc2 {
|
||
|
|
nvidia,pins = "spdif_out_pcc2";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spdif_in_pcc3 {
|
||
|
|
nvidia,pins = "spdif_in_pcc3";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
usb_vbus_en0_pcc4 {
|
||
|
|
nvidia,pins = "usb_vbus_en0_pcc4";
|
||
|
|
nvidia,function = "usb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
usb_vbus_en1_pcc5 {
|
||
|
|
nvidia,pins = "usb_vbus_en1_pcc5";
|
||
|
|
nvidia,function = "usb";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
dp_hpd0_pcc6 {
|
||
|
|
nvidia,pins = "dp_hpd0_pcc6";
|
||
|
|
nvidia,function = "dp";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pcc7 {
|
||
|
|
nvidia,pins = "pcc7";
|
||
|
|
nvidia,function = "rsvd0";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,io-hv = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
spi2_cs1_pdd0 {
|
||
|
|
nvidia,pins = "spi2_cs1_pdd0";
|
||
|
|
nvidia,function = "spi2";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_sck_pee0 {
|
||
|
|
nvidia,pins = "qspi_sck_pee0";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_cs_n_pee1 {
|
||
|
|
nvidia,pins = "qspi_cs_n_pee1";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_io0_pee2 {
|
||
|
|
nvidia,pins = "qspi_io0_pee2";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_io1_pee3 {
|
||
|
|
nvidia,pins = "qspi_io1_pee3";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_io2_pee4 {
|
||
|
|
nvidia,pins = "qspi_io2_pee4";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
qspi_io3_pee5 {
|
||
|
|
nvidia,pins = "qspi_io3_pee5";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
core_pwr_req {
|
||
|
|
nvidia,pins = "core_pwr_req";
|
||
|
|
nvidia,function = "core";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
cpu_pwr_req {
|
||
|
|
nvidia,pins = "cpu_pwr_req";
|
||
|
|
nvidia,function = "cpu";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
pwr_int_n {
|
||
|
|
nvidia,pins = "pwr_int_n";
|
||
|
|
nvidia,function = "pmi";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
clk_32k_in {
|
||
|
|
nvidia,pins = "clk_32k_in";
|
||
|
|
nvidia,function = "clk";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
jtag_rtck {
|
||
|
|
nvidia,pins = "jtag_rtck";
|
||
|
|
nvidia,function = "jtag";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
clk_req {
|
||
|
|
nvidia,pins = "clk_req";
|
||
|
|
nvidia,function = "rsvd1";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
shutdown {
|
||
|
|
nvidia,pins = "shutdown";
|
||
|
|
nvidia,function = "shutdown";
|
||
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
dvfs_pwm_active_state: dvfs_pwm_active {
|
||
|
|
dvfs_pwm_pbb1 {
|
||
|
|
nvidia,pins = "dvfs_pwm_pbb1";
|
||
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
|
||
|
|
dvfs_pwm_pbb1 {
|
||
|
|
nvidia,pins = "dvfs_pwm_pbb1";
|
||
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pwm@7000a000 {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c@7000c400 {
|
||
|
|
status = "okay";
|
||
|
|
clock-frequency = <100000>;
|
||
|
|
|
||
|
|
exp1: gpio@74 {
|
||
|
|
compatible = "ti,tca9539";
|
||
|
|
reg = <0x74>;
|
||
|
|
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
gpio-controller;
|
||
|
|
};
|
||
|
|
|
||
|
|
exp2: gpio@77 {
|
||
|
|
compatible = "ti,tca9539";
|
||
|
|
reg = <0x77>;
|
||
|
|
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
gpio-controller;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* HDMI DDC */
|
||
|
|
hdmi_ddc: i2c@7000c700 {
|
||
|
|
status = "okay";
|
||
|
|
clock-frequency = <100000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sata@70020000 {
|
||
|
|
status = "okay";
|
||
|
|
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hda@70030000 {
|
||
|
|
nvidia,model = "NVIDIA Jetson TX1 HDA";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb@70090000 {
|
||
|
|
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
|
||
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
|
||
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
|
||
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
|
||
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
|
||
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
|
||
|
|
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
|
||
|
|
"usb3-1";
|
||
|
|
dvddio-pex-supply = <&vdd_pex_1v05>;
|
||
|
|
hvddio-pex-supply = <&vdd_1v8>;
|
||
|
|
avdd-usb-supply = <&vdd_3v3_sys>;
|
||
|
|
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
ethernet@1 {
|
||
|
|
reg = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
padctl@7009f000 {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
avdd-pll-utmip-supply = <&vdd_1v8>;
|
||
|
|
avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
|
||
|
|
dvdd-pex-pll-supply = <&vdd_pex_1v05>;
|
||
|
|
hvdd-pex-pll-e-supply = <&vdd_1v8>;
|
||
|
|
|
||
|
|
pads {
|
||
|
|
usb2 {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
lanes {
|
||
|
|
micro_b: usb2-0 {
|
||
|
|
nvidia,function = "xusb";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb2-1 {
|
||
|
|
nvidia,function = "xusb";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb2-2 {
|
||
|
|
nvidia,function = "xusb";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb2-3 {
|
||
|
|
nvidia,function = "xusb";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
lanes {
|
||
|
|
pcie-0 {
|
||
|
|
nvidia,function = "pcie-x1";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie-1 {
|
||
|
|
nvidia,function = "pcie-x4";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie-2 {
|
||
|
|
nvidia,function = "pcie-x4";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie-3 {
|
||
|
|
nvidia,function = "pcie-x4";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie-4 {
|
||
|
|
nvidia,function = "pcie-x4";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie-5 {
|
||
|
|
nvidia,function = "usb3-ss";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie-6 {
|
||
|
|
nvidia,function = "usb3-ss";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sata {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
lanes {
|
||
|
|
sata-0 {
|
||
|
|
nvidia,function = "sata";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
ports {
|
||
|
|
usb2-0 {
|
||
|
|
status = "okay";
|
||
|
|
vbus-supply = <&vdd_usb_vbus_otg>;
|
||
|
|
usb-role-switch;
|
||
|
|
mode = "otg";
|
||
|
|
|
||
|
|
connector {
|
||
|
|
compatible = "gpio-usb-b-connector",
|
||
|
|
"usb-b-connector";
|
||
|
|
label = "micro-USB";
|
||
|
|
type = "micro";
|
||
|
|
vbus-gpios = <&gpio TEGRA_GPIO(Z, 0)
|
||
|
|
GPIO_ACTIVE_LOW>;
|
||
|
|
id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
usb2-1 {
|
||
|
|
status = "okay";
|
||
|
|
vbus-supply = <&vdd_5v0_rtl>;
|
||
|
|
mode = "host";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb2-2 {
|
||
|
|
status = "okay";
|
||
|
|
vbus-supply = <&vdd_usb_vbus>;
|
||
|
|
mode = "host";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb2-3 {
|
||
|
|
status = "okay";
|
||
|
|
mode = "host";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb3-0 {
|
||
|
|
nvidia,usb2-companion = <1>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
usb3-1 {
|
||
|
|
nvidia,usb2-companion = <2>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* MMC/SD */
|
||
|
|
mmc@700b0000 {
|
||
|
|
status = "okay";
|
||
|
|
bus-width = <4>;
|
||
|
|
|
||
|
|
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
|
||
|
|
|
||
|
|
vqmmc-supply = <&vddio_sdmmc>;
|
||
|
|
vmmc-supply = <&vdd_3v3_sd>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usb@700d0000 {
|
||
|
|
status = "okay";
|
||
|
|
phys = <µ_b>;
|
||
|
|
phy-names = "usb2-0";
|
||
|
|
avddio-usb-supply = <&vdd_3v3_sys>;
|
||
|
|
hvdd-usb-supply = <&vdd_1v8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpio-keys {
|
||
|
|
compatible = "gpio-keys";
|
||
|
|
label = "gpio-keys";
|
||
|
|
|
||
|
|
key-power {
|
||
|
|
label = "Power";
|
||
|
|
gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
|
||
|
|
linux,code = <KEY_POWER>;
|
||
|
|
wakeup-source;
|
||
|
|
};
|
||
|
|
|
||
|
|
key-volume-down {
|
||
|
|
label = "Volume Down";
|
||
|
|
gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
|
||
|
|
linux,code = <KEY_VOLUMEDOWN>;
|
||
|
|
};
|
||
|
|
|
||
|
|
key-volume-up {
|
||
|
|
label = "Volume Up";
|
||
|
|
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
|
||
|
|
linux,code = <KEY_VOLUMEUP>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_sys_mux: regulator-vdd-sys-mux {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "VDD_SYS_MUX";
|
||
|
|
regulator-min-microvolt = <5000000>;
|
||
|
|
regulator-max-microvolt = <5000000>;
|
||
|
|
regulator-always-on;
|
||
|
|
regulator-boot-on;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_5v0_sys: regulator-vdd-5v0-sys {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "VDD_5V0_SYS";
|
||
|
|
regulator-min-microvolt = <5000000>;
|
||
|
|
regulator-max-microvolt = <5000000>;
|
||
|
|
regulator-always-on;
|
||
|
|
regulator-boot-on;
|
||
|
|
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_sys_mux>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_3v3_sys: regulator-vdd-3v3-sys {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "VDD_3V3_SYS";
|
||
|
|
regulator-min-microvolt = <3300000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
regulator-always-on;
|
||
|
|
regulator-boot-on;
|
||
|
|
gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_sys_mux>;
|
||
|
|
|
||
|
|
regulator-enable-ramp-delay = <160>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_5v0_io: regulator-vdd-5v0-io {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "VDD_5V0_IO_SYS";
|
||
|
|
regulator-min-microvolt = <5000000>;
|
||
|
|
regulator-max-microvolt = <5000000>;
|
||
|
|
regulator-always-on;
|
||
|
|
regulator-boot-on;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_3v3_sd: regulator-vdd-3v3-sd {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "VDD_3V3_SD";
|
||
|
|
regulator-min-microvolt = <3300000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_3v3_sys>;
|
||
|
|
|
||
|
|
regulator-enable-ramp-delay = <472>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_dsi_csi: regulator-vdd-dsi-csi {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "AVDD_DSI_CSI_1V2";
|
||
|
|
regulator-min-microvolt = <1200000>;
|
||
|
|
regulator-max-microvolt = <1200000>;
|
||
|
|
vin-supply = <&vdd_sys_1v2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_3v3_dis: regulator-vdd-3v3-dis {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "VDD_DIS_3V3_LCD";
|
||
|
|
regulator-min-microvolt = <3300000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
regulator-always-on;
|
||
|
|
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_3v3_sys>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_1v8_dis: regulator-vdd-1v8-dis {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "VDD_LCD_1V8_DIS";
|
||
|
|
regulator-min-microvolt = <1800000>;
|
||
|
|
regulator-max-microvolt = <1800000>;
|
||
|
|
regulator-always-on;
|
||
|
|
gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_1v8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_5v0_rtl: regulator-vdd-5v0-rtl {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "RTL_5V";
|
||
|
|
regulator-min-microvolt = <5000000>;
|
||
|
|
regulator-max-microvolt = <5000000>;
|
||
|
|
gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_5v0_sys>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_usb_vbus: regulator-vdd-usb-vbus {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "USB_VBUS_EN1";
|
||
|
|
regulator-min-microvolt = <5000000>;
|
||
|
|
regulator-max-microvolt = <5000000>;
|
||
|
|
gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_5v0_sys>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_hdmi: regulator-vdd-hdmi {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "VDD_HDMI_5V0";
|
||
|
|
regulator-min-microvolt = <5000000>;
|
||
|
|
regulator-max-microvolt = <5000000>;
|
||
|
|
gpio = <&exp1 12 GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_5v0_sys>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_cam_1v2: regulator-vdd-cam-1v2 {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "vdd-cam-1v2";
|
||
|
|
regulator-min-microvolt = <1200000>;
|
||
|
|
regulator-max-microvolt = <1200000>;
|
||
|
|
gpio = <&exp2 10 GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_3v3_sys>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_cam_2v8: regulator-vdd-cam-2v8 {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "vdd-cam-2v8";
|
||
|
|
regulator-min-microvolt = <2800000>;
|
||
|
|
regulator-max-microvolt = <2800000>;
|
||
|
|
gpio = <&exp1 13 GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_3v3_sys>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_cam_1v8: regulator-vdd-cam-1v8 {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "vdd-cam-1v8";
|
||
|
|
regulator-min-microvolt = <1800000>;
|
||
|
|
regulator-max-microvolt = <1800000>;
|
||
|
|
gpio = <&exp2 9 GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_3v3_sys>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
regulator-name = "USB_VBUS_EN0";
|
||
|
|
regulator-min-microvolt = <5000000>;
|
||
|
|
regulator-max-microvolt = <5000000>;
|
||
|
|
gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
|
||
|
|
enable-active-high;
|
||
|
|
vin-supply = <&vdd_5v0_sys>;
|
||
|
|
};
|
||
|
|
};
|