376 lines
6.2 KiB
Plaintext
376 lines
6.2 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for Marvell Armada 8040 Development board platform
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-8040.dtsi"
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/ {
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model = "Marvell Armada 8040 DB board";
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compatible = "marvell,armada8040-db", "marvell,armada8040",
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"marvell,armada-ap806-quad", "marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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aliases {
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp0_eth2;
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ethernet2 = &cp1_eth0;
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ethernet3 = &cp1_eth1;
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i2c1 = &cp0_i2c0;
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i2c2 = &cp1_i2c0;
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};
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cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
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compatible = "regulator-fixed";
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regulator-name = "cp0-usb3h0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
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};
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cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "cp0-usb3h1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
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};
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cp0_usb3_0_phy: cp0-usb3-0-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp0_reg_usb3_0_vbus>;
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};
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cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
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compatible = "regulator-fixed";
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regulator-name = "cp1-usb3h0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
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};
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cp1_usb3_0_phy: cp1-usb3-0-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp1_reg_usb3_0_vbus>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem";
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reg = <0x200000 0xce0000>;
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};
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};
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};
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};
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/* Accessible over the mini-USB CON9 connector on the main board */
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&uart0 {
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status = "okay";
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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};
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/* CON6 on CP0 expansion */
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&cp0_pcie0 {
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phys = <&cp0_comphy0 0>;
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phy-names = "cp0-pcie0-x1-phy";
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status = "okay";
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};
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/* CON5 on CP0 expansion */
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&cp0_pcie2 {
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phys = <&cp0_comphy5 2>;
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phy-names = "cp0-pcie2-x1-phy";
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status = "okay";
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};
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&cp0_i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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/* U31 */
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expander0: pca9555@21 {
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x21>;
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};
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/* U25 */
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expander1: pca9555@25 {
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x25>;
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};
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};
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/* CON4 on CP0 expansion */
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&cp0_sata0 {
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status = "okay";
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sata-port@0 {
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phys = <&cp0_comphy1 0>;
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phy-names = "cp0-sata0-0-phy";
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};
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sata-port@1 {
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phys = <&cp0_comphy3 1>;
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phy-names = "cp0-sata0-1-phy";
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};
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};
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/* CON9 on CP0 expansion */
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&cp0_utmi {
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status = "okay";
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};
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&cp0_usb3_0 {
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usb-phy = <&cp0_usb3_0_phy>;
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phys = <&cp0_utmi0>;
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phy-names = "utmi";
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dr_mode = "host";
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status = "okay";
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};
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&cp0_comphy4 {
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cp0_usbh1_con: connector {
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compatible = "usb-a-connector";
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phy-supply = <&cp0_reg_usb3_1_vbus>;
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};
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};
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/* CON10 on CP0 expansion */
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&cp0_usb3_1 {
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phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
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phy-names = "usb", "utmi";
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dr_mode = "host";
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status = "okay";
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};
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&cp0_mdio {
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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&cp0_eth0 {
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status = "okay";
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phy-mode = "10gbase-r";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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&cp0_eth2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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/* CON6 on CP1 expansion */
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&cp1_pcie0 {
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phys = <&cp1_comphy0 0>;
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phy-names = "cp1-pcie0-x1-phy";
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status = "okay";
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};
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/* CON7 on CP1 expansion */
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&cp1_pcie1 {
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phys = <&cp1_comphy4 1>;
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phy-names = "cp1-pcie1-x1-phy";
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status = "okay";
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};
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/* CON5 on CP1 expansion */
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&cp1_pcie2 {
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phys = <&cp1_comphy5 2>;
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phy-names = "cp1-pcie2-x1-phy";
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status = "okay";
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};
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&cp1_i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&cp1_spi1 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <20000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Boot";
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reg = <0x0 0x200000>;
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};
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partition@200000 {
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label = "Filesystem";
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reg = <0x200000 0xd00000>;
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};
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partition@f00000 {
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label = "Boot_2nd";
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reg = <0xf00000 0x100000>;
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};
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};
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};
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};
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/*
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* Proper NAND usage will require DPR-76 to be in position 1-2, which disables
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* MDIO signal of CP1.
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*/
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&cp1_nand_controller {
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pinctrl-0 = <&nand_pins>, <&nand_rb>;
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pinctrl-names = "default";
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nand@0 {
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reg = <0>;
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nand-rb = <0>;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x200000>;
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};
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partition@200000 {
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label = "Linux";
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reg = <0x200000 0xe00000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x1000000 0x3f000000>;
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};
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};
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};
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};
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/* CON4 on CP1 expansion */
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&cp1_sata0 {
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status = "okay";
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sata-port@0 {
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phys = <&cp1_comphy1 0>;
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phy-names = "cp1-sata0-0-phy";
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};
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sata-port@1 {
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phys = <&cp1_comphy3 1>;
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phy-names = "cp1-sata0-1-phy";
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};
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};
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&cp1_utmi {
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status = "okay";
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};
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/* CON9 on CP1 expansion */
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&cp1_usb3_0 {
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usb-phy = <&cp1_usb3_0_phy>;
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phys = <&cp1_utmi0>;
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phy-names = "utmi";
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dr_mode = "host";
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status = "okay";
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};
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/* CON10 on CP1 expansion */
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&cp1_usb3_1 {
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phys = <&cp1_utmi1>;
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phy-names = "utmi";
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status = "okay";
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};
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&cp1_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&cp1_ethernet {
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status = "okay";
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};
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&cp1_eth0 {
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status = "okay";
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phy-mode = "10gbase-r";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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&cp1_eth1 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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&ap_sdhci0 {
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status = "okay";
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bus-width = <4>;
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non-removable;
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};
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&cp0_sdhci0 {
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status = "okay";
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bus-width = <8>;
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non-removable;
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};
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