115 lines
2.5 KiB
Plaintext
115 lines
2.5 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 NXP
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*/
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/dts-v1/;
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#include "imx93.dtsi"
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/ {
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model = "NXP i.MX93 11X11 EVK board";
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compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
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chosen {
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stdout-path = &lpuart1;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&mu1 {
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status = "okay";
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};
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&mu2 {
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status = "okay";
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};
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&lpuart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1>;
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pinctrl-2 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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no-sdio;
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no-mmc;
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};
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&iomuxc {
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
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MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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};
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