318 lines
7.5 KiB
Plaintext
318 lines
7.5 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
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*/
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#include "imx8mq.dtsi"
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/ {
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reg_vdd_3v3: regulator-vdd-3v3 {
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compatible = "regulator-fixed";
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regulator-always-on;
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regulator-name = "vdd_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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reset-assert-us = <2000>;
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};
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <400000>;
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status = "okay";
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pmic: pmic@8 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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eeprom@50 {
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compatible = "atmel,24c01";
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reg = <0x50>;
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status = "okay";
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};
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};
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&pgc_gpu{
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power-supply = <&sw1a_reg>;
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};
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&pgc_vpu {
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power-supply = <&sw1c_reg>;
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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/* SPI flash; not assembled by default */
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spi_flash: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "micron,n25q256a", "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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status = "disabled";
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};
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};
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&uart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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assigned-clock-rates = <25000000>;
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status = "okay";
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};
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&uart4 { /* ublox BT */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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assigned-clock-rates = <80000000>;
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status = "okay";
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};
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&usdhc1 {
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74
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MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16
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MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
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MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
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MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
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MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
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MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
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MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
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>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
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MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
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MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
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>;
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};
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};
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