231 lines
6.4 KiB
Plaintext
231 lines
6.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd.
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*
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* ARMv8 Foundation model DTS
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/memreserve/ 0x80000000 0x00010000;
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/ {
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model = "Foundation-v8A";
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compatible = "arm,foundation-aarch64", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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next-level-cache = <&L2_0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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next-level-cache = <&L2_0>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <100000000>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog@2a440000 {
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compatible = "arm,sbsa-gwdt";
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reg = <0x0 0x2a440000 0 0x1000>,
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<0x0 0x2a450000 0 0x1000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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timeout-sec = <30>;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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bus@8000000 {
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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ethernet@202000000 {
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compatible = "smsc,lan91c111";
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reg = <2 0x02000000 0x10000>;
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interrupts = <15>;
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};
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iofpga-bus@300000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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v2m_sysreg: sysreg@10000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x010000 0x1000>;
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};
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v2m_serial0: serial@90000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x090000 0x1000>;
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interrupts = <5>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: serial@a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a0000 0x1000>;
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interrupts = <6>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial2: serial@b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b0000 0x1000>;
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interrupts = <7>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial3: serial@c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c0000 0x1000>;
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interrupts = <8>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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virtio@130000 {
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compatible = "virtio,mmio";
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reg = <0x130000 0x200>;
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interrupts = <42>;
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};
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};
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};
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};
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