118 lines
1.7 KiB
Plaintext
118 lines
1.7 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022, Intel Corporation
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*/
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#include "socfpga_stratix10.dtsi"
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/ {
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model = "SOCFPGA Stratix 10 SWVP";
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compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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timer0 = &timer0;
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timer1 = &timer1;
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timer2 = &timer2;
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timer3 = &timer3;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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};
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chosen {
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stdout-path = "serial1:115200n8";
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linux,initrd-start = <0x10000000>;
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linux,initrd-end = <0x125c8324>;
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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};
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&cpu0 {
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x0000fff8>;
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};
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&cpu1 {
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x0000fff8>;
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};
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&cpu2 {
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x0000fff8>;
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};
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&cpu3 {
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x0000fff8>;
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};
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&osc1 {
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clock-frequency = <25000000>;
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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phy-addr = <0xffffffff>;
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snps,max-mtu = <0x0>;
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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phy-addr = <0xffffffff>;
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};
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&gmac2 {
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status = "okay";
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phy-mode = "rgmii";
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phy-addr = <0xffffffff>;
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};
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&mmc {
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status = "okay";
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altr,dw-mshc-ciu-div = <0x3>;
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altr,dw-mshc-sdr-timing = <0x0 0x3>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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broken-cd;
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bus-width = <4>;
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&usb0 {
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clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
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status = "okay";
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};
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&usb1 {
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clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
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status = "okay";
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};
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&rst {
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altr,modrst-offset = <0x20>;
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};
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&sysmgr {
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reg = <0xffd12000 0x1000>;
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interrupts = <0x0 0x10 0x4>;
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cpu1-start-addr = <0xffd06230>;
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};
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