541 lines
13 KiB
Plaintext
541 lines
13 KiB
Plaintext
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||
|
|
/*
|
||
|
|
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||
|
|
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||
|
|
*/
|
||
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||
|
|
#include <dt-bindings/clock/stm32mp13-clks.h>
|
||
|
|
#include <dt-bindings/reset/stm32mp13-resets.h>
|
||
|
|
|
||
|
|
/ {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
cpus {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
cpu0: cpu@0 {
|
||
|
|
compatible = "arm,cortex-a7";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
arm-pmu {
|
||
|
|
compatible = "arm,cortex-a7-pmu";
|
||
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-affinity = <&cpu0>;
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
};
|
||
|
|
|
||
|
|
firmware {
|
||
|
|
optee {
|
||
|
|
method = "smc";
|
||
|
|
compatible = "linaro,optee-tz";
|
||
|
|
};
|
||
|
|
|
||
|
|
scmi: scmi {
|
||
|
|
compatible = "linaro,scmi-optee";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
linaro,optee-channel-id = <0>;
|
||
|
|
shmem = <&scmi_shm>;
|
||
|
|
|
||
|
|
scmi_clk: protocol@14 {
|
||
|
|
reg = <0x14>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
scmi_reset: protocol@16 {
|
||
|
|
reg = <0x16>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
intc: interrupt-controller@a0021000 {
|
||
|
|
compatible = "arm,cortex-a7-gic";
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
interrupt-controller;
|
||
|
|
reg = <0xa0021000 0x1000>,
|
||
|
|
<0xa0022000 0x2000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
psci {
|
||
|
|
compatible = "arm,psci-1.0";
|
||
|
|
method = "smc";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer {
|
||
|
|
compatible = "arm,armv7-timer";
|
||
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
always-on;
|
||
|
|
};
|
||
|
|
|
||
|
|
soc {
|
||
|
|
compatible = "simple-bus";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
interrupt-parent = <&intc>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
scmi_sram: sram@2ffff000 {
|
||
|
|
compatible = "mmio-sram";
|
||
|
|
reg = <0x2ffff000 0x1000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0x2ffff000 0x1000>;
|
||
|
|
|
||
|
|
scmi_shm: scmi-sram@0 {
|
||
|
|
compatible = "arm,scmi-shmem";
|
||
|
|
reg = <0 0x80>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
spi2: spi@4000b000 {
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x4000b000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI2_K>;
|
||
|
|
resets = <&rcc SPI2_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 39 0x400 0x01>,
|
||
|
|
<&dmamux1 40 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi3: spi@4000c000 {
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x4000c000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI3_K>;
|
||
|
|
resets = <&rcc SPI3_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 61 0x400 0x01>,
|
||
|
|
<&dmamux1 62 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart4: serial@40010000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x40010000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc UART4_K>;
|
||
|
|
resets = <&rcc UART4_R>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1: i2c@40012000 {
|
||
|
|
compatible = "st,stm32mp13-i2c";
|
||
|
|
reg = <0x40012000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C1_K>;
|
||
|
|
resets = <&rcc I2C1_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 33 0x400 0x1>,
|
||
|
|
<&dmamux1 34 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x1>;
|
||
|
|
i2c-analog-filter;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2: i2c@40013000 {
|
||
|
|
compatible = "st,stm32mp13-i2c";
|
||
|
|
reg = <0x40013000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C2_K>;
|
||
|
|
resets = <&rcc I2C2_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 35 0x400 0x1>,
|
||
|
|
<&dmamux1 36 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x2>;
|
||
|
|
i2c-analog-filter;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi1: spi@44004000 {
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x44004000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI1_K>;
|
||
|
|
resets = <&rcc SPI1_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 37 0x400 0x01>,
|
||
|
|
<&dmamux1 38 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dma1: dma-controller@48000000 {
|
||
|
|
compatible = "st,stm32-dma";
|
||
|
|
reg = <0x48000000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc DMA1>;
|
||
|
|
resets = <&rcc DMA1_R>;
|
||
|
|
#dma-cells = <4>;
|
||
|
|
st,mem2mem;
|
||
|
|
dma-requests = <8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
dma2: dma-controller@48001000 {
|
||
|
|
compatible = "st,stm32-dma";
|
||
|
|
reg = <0x48001000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc DMA2>;
|
||
|
|
resets = <&rcc DMA2_R>;
|
||
|
|
#dma-cells = <4>;
|
||
|
|
st,mem2mem;
|
||
|
|
dma-requests = <8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
dmamux1: dma-router@48002000 {
|
||
|
|
compatible = "st,stm32h7-dmamux";
|
||
|
|
reg = <0x48002000 0x40>;
|
||
|
|
clocks = <&rcc DMAMUX1>;
|
||
|
|
resets = <&rcc DMAMUX1_R>;
|
||
|
|
#dma-cells = <3>;
|
||
|
|
dma-masters = <&dma1 &dma2>;
|
||
|
|
dma-requests = <128>;
|
||
|
|
dma-channels = <16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
spi4: spi@4c002000 {
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x4c002000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI4_K>;
|
||
|
|
resets = <&rcc SPI4_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 83 0x400 0x01>,
|
||
|
|
<&dmamux1 84 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi5: spi@4c003000 {
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x4c003000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI5_K>;
|
||
|
|
resets = <&rcc SPI5_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 85 0x400 0x01>,
|
||
|
|
<&dmamux1 86 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c3: i2c@4c004000 {
|
||
|
|
compatible = "st,stm32mp13-i2c";
|
||
|
|
reg = <0x4c004000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C3_K>;
|
||
|
|
resets = <&rcc I2C3_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 73 0x400 0x1>,
|
||
|
|
<&dmamux1 74 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x4>;
|
||
|
|
i2c-analog-filter;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c4: i2c@4c005000 {
|
||
|
|
compatible = "st,stm32mp13-i2c";
|
||
|
|
reg = <0x4c005000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C4_K>;
|
||
|
|
resets = <&rcc I2C4_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 75 0x400 0x1>,
|
||
|
|
<&dmamux1 76 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x8>;
|
||
|
|
i2c-analog-filter;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c5: i2c@4c006000 {
|
||
|
|
compatible = "st,stm32mp13-i2c";
|
||
|
|
reg = <0x4c006000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C5_K>;
|
||
|
|
resets = <&rcc I2C5_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 115 0x400 0x1>,
|
||
|
|
<&dmamux1 116 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x10>;
|
||
|
|
i2c-analog-filter;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
rcc: rcc@50000000 {
|
||
|
|
compatible = "st,stm32mp13-rcc", "syscon";
|
||
|
|
reg = <0x50000000 0x1000>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||
|
|
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||
|
|
<&scmi_clk CK_SCMI_HSI>,
|
||
|
|
<&scmi_clk CK_SCMI_CSI>,
|
||
|
|
<&scmi_clk CK_SCMI_LSE>,
|
||
|
|
<&scmi_clk CK_SCMI_LSI>;
|
||
|
|
};
|
||
|
|
|
||
|
|
exti: interrupt-controller@5000d000 {
|
||
|
|
compatible = "st,stm32mp13-exti", "syscon";
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x5000d000 0x400>;
|
||
|
|
};
|
||
|
|
|
||
|
|
syscfg: syscon@50020000 {
|
||
|
|
compatible = "st,stm32mp157-syscfg", "syscon";
|
||
|
|
reg = <0x50020000 0x400>;
|
||
|
|
clocks = <&rcc SYSCFG>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mdma: dma-controller@58000000 {
|
||
|
|
compatible = "st,stm32h7-mdma";
|
||
|
|
reg = <0x58000000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc MDMA>;
|
||
|
|
#dma-cells = <5>;
|
||
|
|
dma-channels = <32>;
|
||
|
|
dma-requests = <48>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sdmmc1: mmc@58005000 {
|
||
|
|
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
||
|
|
arm,primecell-periphid = <0x20253180>;
|
||
|
|
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "cmd_irq";
|
||
|
|
clocks = <&rcc SDMMC1_K>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
resets = <&rcc SDMMC1_R>;
|
||
|
|
cap-sd-highspeed;
|
||
|
|
cap-mmc-highspeed;
|
||
|
|
max-frequency = <130000000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdmmc2: mmc@58007000 {
|
||
|
|
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
||
|
|
arm,primecell-periphid = <0x20253180>;
|
||
|
|
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "cmd_irq";
|
||
|
|
clocks = <&rcc SDMMC2_K>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
resets = <&rcc SDMMC2_R>;
|
||
|
|
cap-sd-highspeed;
|
||
|
|
cap-mmc-highspeed;
|
||
|
|
max-frequency = <130000000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
iwdg2: watchdog@5a002000 {
|
||
|
|
compatible = "st,stm32mp1-iwdg";
|
||
|
|
reg = <0x5a002000 0x400>;
|
||
|
|
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||
|
|
clock-names = "pclk", "lsi";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
rtc: rtc@5c004000 {
|
||
|
|
compatible = "st,stm32mp1-rtc";
|
||
|
|
reg = <0x5c004000 0x400>;
|
||
|
|
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&scmi_clk CK_SCMI_RTCAPB>,
|
||
|
|
<&scmi_clk CK_SCMI_RTC>;
|
||
|
|
clock-names = "pclk", "rtc_ck";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
bsec: efuse@5c005000 {
|
||
|
|
compatible = "st,stm32mp15-bsec";
|
||
|
|
reg = <0x5c005000 0x400>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
part_number_otp: part_number_otp@4 {
|
||
|
|
reg = <0x4 0x2>;
|
||
|
|
bits = <0 12>;
|
||
|
|
};
|
||
|
|
ts_cal1: calib@5c {
|
||
|
|
reg = <0x5c 0x2>;
|
||
|
|
};
|
||
|
|
ts_cal2: calib@5e {
|
||
|
|
reg = <0x5e 0x2>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Break node order to solve dependency probe issue between
|
||
|
|
* pinctrl and exti.
|
||
|
|
*/
|
||
|
|
pinctrl: pinctrl@50002000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "st,stm32mp135-pinctrl";
|
||
|
|
ranges = <0 0x50002000 0x8400>;
|
||
|
|
interrupt-parent = <&exti>;
|
||
|
|
st,syscfg = <&exti 0x60 0xff>;
|
||
|
|
pins-are-numbered;
|
||
|
|
|
||
|
|
gpioa: gpio@50002000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x0 0x400>;
|
||
|
|
clocks = <&rcc GPIOA>;
|
||
|
|
st,bank-name = "GPIOA";
|
||
|
|
ngpios = <16>;
|
||
|
|
gpio-ranges = <&pinctrl 0 0 16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiob: gpio@50003000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x1000 0x400>;
|
||
|
|
clocks = <&rcc GPIOB>;
|
||
|
|
st,bank-name = "GPIOB";
|
||
|
|
ngpios = <16>;
|
||
|
|
gpio-ranges = <&pinctrl 0 16 16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioc: gpio@50004000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x2000 0x400>;
|
||
|
|
clocks = <&rcc GPIOC>;
|
||
|
|
st,bank-name = "GPIOC";
|
||
|
|
ngpios = <16>;
|
||
|
|
gpio-ranges = <&pinctrl 0 32 16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiod: gpio@50005000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x3000 0x400>;
|
||
|
|
clocks = <&rcc GPIOD>;
|
||
|
|
st,bank-name = "GPIOD";
|
||
|
|
ngpios = <16>;
|
||
|
|
gpio-ranges = <&pinctrl 0 48 16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioe: gpio@50006000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x4000 0x400>;
|
||
|
|
clocks = <&rcc GPIOE>;
|
||
|
|
st,bank-name = "GPIOE";
|
||
|
|
ngpios = <16>;
|
||
|
|
gpio-ranges = <&pinctrl 0 64 16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiof: gpio@50007000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x5000 0x400>;
|
||
|
|
clocks = <&rcc GPIOF>;
|
||
|
|
st,bank-name = "GPIOF";
|
||
|
|
ngpios = <16>;
|
||
|
|
gpio-ranges = <&pinctrl 0 80 16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiog: gpio@50008000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x6000 0x400>;
|
||
|
|
clocks = <&rcc GPIOG>;
|
||
|
|
st,bank-name = "GPIOG";
|
||
|
|
ngpios = <16>;
|
||
|
|
gpio-ranges = <&pinctrl 0 96 16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioh: gpio@50009000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x7000 0x400>;
|
||
|
|
clocks = <&rcc GPIOH>;
|
||
|
|
st,bank-name = "GPIOH";
|
||
|
|
ngpios = <15>;
|
||
|
|
gpio-ranges = <&pinctrl 0 112 15>;
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioi: gpio@5000a000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x8000 0x400>;
|
||
|
|
clocks = <&rcc GPIOI>;
|
||
|
|
st,bank-name = "GPIOI";
|
||
|
|
ngpios = <8>;
|
||
|
|
gpio-ranges = <&pinctrl 0 128 8>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|