529 lines
9.5 KiB
Plaintext
529 lines
9.5 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Fievel Rev 0+ board device tree source
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*
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* Copyright 2016 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron.dtsi"
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#include "rk3288-veyron-analog-audio.dtsi"
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/ {
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model = "Google Fievel";
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compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
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"google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
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"google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
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"google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
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"google,veyron-fievel-rev0", "google,veyron-fievel",
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"google,veyron", "rockchip,rk3288";
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vccsys: vccsys {
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compatible = "regulator-fixed";
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regulator-name = "vccsys";
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regulator-boot-on;
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regulator-always-on;
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};
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/*
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* vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys,
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* enabled by vcc_18
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*/
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vcc33_io: vcc33-io {
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compatible = "regulator-fixed";
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vcc33_io";
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};
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vcc5_host1: vcc5-host1-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&hub_usb1_pwr_en>;
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regulator-name = "vcc5_host1";
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regulator-always-on;
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regulator-boot-on;
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};
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vcc5_host2: vcc5-host2-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&hub_usb2_pwr_en>;
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regulator-name = "vcc5_host2";
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regulator-always-on;
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regulator-boot-on;
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};
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vcc5v_otg: vcc5v-otg-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&usb_otg_pwr_en>;
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regulator-name = "vcc5_otg";
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regulator-always-on;
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regulator-boot-on;
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};
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ext_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "ext_gmac";
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};
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};
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&gmac {
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status = "okay";
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assigned-clocks = <&cru SCLK_MAC>;
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assigned-clock-parents = <&ext_gmac>;
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clock_in_out = "input";
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phy-handle = <ðphy>;
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phy-mode = "rgmii";
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phy-supply = <&vcc33_lan>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
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rx_delay = <0x10>;
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tx_delay = <0x30>;
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/*
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* Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low)
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* with a 30ms settling time.
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*/
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snps,reset-gpio = <&gpio4 RK_PB0 0>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 30000>;
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wakeup-source;
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mdio0 {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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&rk808 {
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dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
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<&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
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vcc6-supply = <&vcc33_sys>;
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vcc10-supply = <&vcc33_sys>;
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vcc11-supply = <&vcc_5v>;
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vcc12-supply = <&vcc33_sys>;
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regulators {
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/delete-node/ LDO_REG1;
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/*
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* According to the schematic, vcc18_lcdt is for
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* HDMI_AVDD_1V8
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*/
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vcc18_lcdt: LDO_REG2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vdd18_lcdt";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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/*
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* This is not a pwren anymore, but the real power supply,
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* vdd10_lcd for HDMI_AVDD_1V0
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*/
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vdd10_lcd: LDO_REG7 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-name = "vdd10_lcd";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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/* for usb camera */
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vcc33_ccd: LDO_REG8 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc33_ccd";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc33_lan: SWITCH_REG2 {
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regulator-name = "vcc33_lan";
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};
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};
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};
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&sdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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btmrvl: btmrvl@2 {
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compatible = "marvell,sd8897-bt";
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reg = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
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marvell,wakeup-pin = /bits/ 16 <13>;
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pinctrl-names = "default";
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pinctrl-0 = <&bt_host_wake_l>;
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};
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc50_hdmi_en>;
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};
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&vcc_5v {
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enable-active-high;
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gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&drv_5v>;
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};
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&gpio0 {
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gpio-line-names = "PMIC_SLEEP_AP",
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"DDRIO_PWROFF",
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"DDRIO_RETEN",
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"TS3A227E_INT_L",
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"PMIC_INT_L",
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"PWR_KEY_L",
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"HUB_USB1_nFALUT",
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"PHY_PMEB",
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"PHY_INT",
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/*
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* RECOVERY_SW_L is Chrome OS ABI. Schematics call
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* it REC_MODE_L.
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*/
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"RECOVERY_SW_L",
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"OTP_OUT",
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"",
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"USB_OTG_POWER_EN",
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"AP_WARM_RESET_H",
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"USB_OTG_nFALUT",
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"I2C0_SDA_PMIC",
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"I2C0_SCL_PMIC",
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"DEVMODE_L",
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"USB_INT";
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};
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&gpio2 {
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gpio-line-names = "CONFIG0",
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"CONFIG1",
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"CONFIG2",
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"",
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"",
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"",
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"",
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"CONFIG3",
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"",
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"EMMC_RST_L",
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"",
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"",
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"BL_PWR_EN",
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"",
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"TOUCH_INT",
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"TOUCH_RST",
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"I2C3_SCL_TP",
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"I2C3_SDA_TP";
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};
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&gpio3 {
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gpio-line-names = "FLASH0_D0",
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"FLASH0_D1",
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"FLASH0_D2",
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"FLASH0_D3",
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"FLASH0_D4",
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"FLASH0_D5",
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"FLASH0_D6",
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"FLASH0_D7",
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"VCC5V_GOOD_H",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"FLASH0_CS2/EMMC_CMD",
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"",
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"FLASH0_DQS/EMMC_CLKO",
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"",
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"",
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"",
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"",
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"",
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"PHY_TXD2",
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"PHY_TXD3",
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"MAC_RXD2",
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"MAC_RXD3",
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"PHY_TXD0",
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"PHY_TXD1",
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"MAC_RXD0",
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"MAC_RXD1";
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};
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&gpio4 {
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gpio-line-names = "MAC_MDC",
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"MAC_RXDV",
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"MAC_RXER",
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"MAC_CLK",
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"PHY_TXEN",
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"MAC_MDIO",
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"MAC_RXCLK",
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"",
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"PHY_RST",
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"PHY_TXCLK",
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"",
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"",
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"",
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"",
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"",
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"",
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"UART0_RXD",
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"UART0_TXD",
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"UART0_CTS_L",
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"UART0_RTS_L",
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"SDIO0_D0",
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"SDIO0_D1",
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"SDIO0_D2",
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"SDIO0_D3",
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"SDIO0_CMD",
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"SDIO0_CLK",
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"BT_DEV_WAKE",
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"",
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"WIFI_ENABLE_H",
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"BT_ENABLE_L",
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"WIFI_HOST_WAKE",
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"BT_HOST_WAKE";
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};
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&gpio5 {
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gpio-line-names = "",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"USB_OTG_CTL1",
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"HUB_USB2_CTL1",
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"HUB_USB2_PWR_EN",
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"HUB_USB_ILIM_SEL",
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"USB_OTG_STATUS_L",
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"HUB_USB1_CTL1",
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"HUB_USB1_PWR_EN",
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"VCC50_HDMI_EN";
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};
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&gpio6 {
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gpio-line-names = "I2S0_SCLK",
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"I2S0_LRCK_RX",
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"I2S0_LRCK_TX",
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"I2S0_SDI",
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"I2S0_SDO0",
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"HP_DET_H",
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"",
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"INT_CODEC",
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"I2S0_CLK",
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"I2C2_SDA",
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"I2C2_SCL",
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"MICDET",
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"",
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"",
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"",
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"",
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"HUB_USB2_nFALUT",
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"USB_OTG_ILIM_SEL";
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};
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&gpio7 {
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gpio-line-names = "LCD_BL_PWM",
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"PWM_LOG",
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"BL_EN",
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"PWR_LED1",
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"TPM_INT_H",
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"SPK_ON",
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/*
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* AP_FLASH_WP_L is Chrome OS ABI. Schematics call
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* it FW_WP_AP.
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*/
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"AP_FLASH_WP_L",
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"",
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||
|
|
|
||
|
|
"CPU_NMI",
|
||
|
|
"DVSOK",
|
||
|
|
"",
|
||
|
|
"EDP_HPD",
|
||
|
|
"DVS1",
|
||
|
|
"",
|
||
|
|
"LCD_EN",
|
||
|
|
"DVS2",
|
||
|
|
|
||
|
|
"HDMI_CEC",
|
||
|
|
"I2C4_SDA",
|
||
|
|
"I2C4_SCL",
|
||
|
|
"I2C5_SDA_HDMI",
|
||
|
|
"I2C5_SCL_HDMI",
|
||
|
|
"5V_DRV",
|
||
|
|
"UART2_RXD",
|
||
|
|
"UART2_TXD";
|
||
|
|
};
|
||
|
|
|
||
|
|
&gpio8 {
|
||
|
|
gpio-line-names = "RAM_ID0",
|
||
|
|
"RAM_ID1",
|
||
|
|
"RAM_ID2",
|
||
|
|
"RAM_ID3",
|
||
|
|
"I2C1_SDA_TPM",
|
||
|
|
"I2C1_SCL_TPM",
|
||
|
|
"SPI2_CLK",
|
||
|
|
"SPI2_CS0",
|
||
|
|
|
||
|
|
"SPI2_RXD",
|
||
|
|
"SPI2_TXD";
|
||
|
|
};
|
||
|
|
|
||
|
|
&pinctrl {
|
||
|
|
pinctrl-names = "default", "sleep";
|
||
|
|
pinctrl-0 = <
|
||
|
|
/* Common for sleep and wake, but no owners */
|
||
|
|
&ddr0_retention
|
||
|
|
&ddrio_pwroff
|
||
|
|
&global_pwroff
|
||
|
|
|
||
|
|
/* For usb bc1.2 */
|
||
|
|
&usb_otg_ilim_sel
|
||
|
|
&usb_usb_ilim_sel
|
||
|
|
|
||
|
|
/* Wake only */
|
||
|
|
&bt_dev_wake_awake
|
||
|
|
&pwr_led1_on
|
||
|
|
>;
|
||
|
|
|
||
|
|
pinctrl-1 = <
|
||
|
|
/* Common for sleep and wake, but no owners */
|
||
|
|
&ddr0_retention
|
||
|
|
&ddrio_pwroff
|
||
|
|
&global_pwroff
|
||
|
|
|
||
|
|
/* For usb bc1.2 */
|
||
|
|
&usb_otg_ilim_sel
|
||
|
|
&usb_usb_ilim_sel
|
||
|
|
|
||
|
|
/* Sleep only */
|
||
|
|
&bt_dev_wake_sleep
|
||
|
|
&pwr_led1_blink
|
||
|
|
>;
|
||
|
|
|
||
|
|
buck-5v {
|
||
|
|
drv_5v: drv-5v {
|
||
|
|
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
gmac {
|
||
|
|
phy_rst: phy-rst {
|
||
|
|
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
|
||
|
|
};
|
||
|
|
|
||
|
|
phy_pmeb: phy-pmeb {
|
||
|
|
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||
|
|
};
|
||
|
|
|
||
|
|
phy_int: phy-int {
|
||
|
|
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
hdmi {
|
||
|
|
vcc50_hdmi_en: vcc50-hdmi-en {
|
||
|
|
rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
leds {
|
||
|
|
pwr_led1_on: pwr-led1-on {
|
||
|
|
rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pwr_led1_blink: pwr-led1-blink {
|
||
|
|
rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pmic {
|
||
|
|
dvs_1: dvs-1 {
|
||
|
|
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||
|
|
};
|
||
|
|
|
||
|
|
dvs_2: dvs-2 {
|
||
|
|
rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
usb-bc12 {
|
||
|
|
usb_otg_ilim_sel: usb-otg-ilim-sel {
|
||
|
|
rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usb_usb_ilim_sel: usb-usb-ilim-sel {
|
||
|
|
rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
usb-host {
|
||
|
|
hub_usb1_pwr_en: hub_usb1_pwr_en {
|
||
|
|
rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hub_usb2_pwr_en: hub_usb2_pwr_en {
|
||
|
|
rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usb_otg_pwr_en: usb_otg_pwr_en {
|
||
|
|
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|