532 lines
11 KiB
Plaintext
532 lines
11 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-apq8084.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm APQ 8084";
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compatible = "qcom,apq8084";
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interrupt-parent = <&intc>;
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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smem_mem: smem_region@fa00000 {
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reg = <0xfa00000 0x200000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <0>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <1>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <2>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <3>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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cpu-idle-states = <&CPU_SPC>;
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};
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L2: l2-cache {
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compatible = "qcom,arch-cache";
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cache-level = <2>;
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qcom,saw = <&saw_l2>;
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};
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idle-states {
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CPU_SPC: spc {
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compatible = "qcom,idle-state-spc",
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"arm,idle-state";
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entry-latency-us = <150>;
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exit-latency-us = <200>;
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min-residency-us = <2000>;
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};
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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firmware {
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scm {
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compatible = "qcom,scm-apq8084", "qcom,scm";
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clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
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clock-names = "core", "bus", "iface";
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};
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};
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thermal-zones {
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cpu0-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 5>;
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trips {
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cpu_alert0: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu1-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 6>;
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trips {
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cpu_alert1: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit1: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu2-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 7>;
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trips {
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cpu_alert2: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit2: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu3-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens 8>;
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trips {
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cpu_alert3: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit3: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <GIC_PPI 7 0xf04>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 2 0xf08>,
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<GIC_PPI 3 0xf08>,
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<GIC_PPI 4 0xf08>,
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<GIC_PPI 1 0xf08>;
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clock-frequency = <19200000>;
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};
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smem {
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compatible = "qcom,smem";
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0xf9000000 0x1000>,
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<0xf9002000 0x1000>;
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};
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apcs: syscon@f9011000 {
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compatible = "syscon";
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reg = <0xf9011000 0x1000>;
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};
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sram@fc190000 {
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compatible = "qcom,apq8084-rpm-stats";
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reg = <0xfc190000 0x10000>;
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};
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qfprom: qfprom@fc4bc000 {
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compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
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reg = <0xfc4bc000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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tsens_calib: calib@d0 {
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reg = <0xd0 0x18>;
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};
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tsens_backup: backup@440 {
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reg = <0x440 0x10>;
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};
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};
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tsens: thermal-sensor@fc4a8000 {
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compatible = "qcom,msm8974-tsens";
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reg = <0xfc4a9000 0x1000>, /* TM */
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<0xfc4a8000 0x1000>; /* SROT */
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nvmem-cells = <&tsens_calib>, <&tsens_backup>;
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nvmem-cell-names = "calib", "calib_backup";
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#qcom,sensors = <11>;
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#thermal-sensor-cells = <1>;
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};
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timer@f9020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf9020000 0x1000>;
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clock-frequency = <19200000>;
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frame@f9021000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9021000 0x1000>,
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<0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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};
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frame@f9028000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9028000 0x1000>;
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status = "disabled";
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};
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};
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saw0: power-controller@f9089000 {
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compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
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};
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saw1: power-controller@f9099000 {
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compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
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};
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saw2: power-controller@f90a9000 {
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compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
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};
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saw3: power-controller@f90b9000 {
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compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
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};
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saw_l2: power-controller@f9012000 {
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compatible = "qcom,saw2";
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reg = <0xf9012000 0x1000>;
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regulator;
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};
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acc0: clock-controller@f9088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf9088000 0x1000>,
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<0xf9008000 0x1000>;
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};
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acc1: clock-controller@f9098000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf9098000 0x1000>,
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<0xf9008000 0x1000>;
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};
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acc2: clock-controller@f90a8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf90a8000 0x1000>,
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<0xf9008000 0x1000>;
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};
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acc3: clock-controller@f90b8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf90b8000 0x1000>,
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<0xf9008000 0x1000>;
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};
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restart@fc4ab000 {
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compatible = "qcom,pshold";
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reg = <0xfc4ab000 0x4>;
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};
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gcc: clock-controller@fc400000 {
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compatible = "qcom,gcc-apq8084";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0xfc400000 0x4000>;
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};
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tcsr_mutex: hwlock@fd484000 {
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|
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compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
|
||
|
|
reg = <0xfd484000 0x1000>;
|
||
|
|
#hwlock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
rpm_msg_ram: memory@fc428000 {
|
||
|
|
compatible = "qcom,rpm-msg-ram";
|
||
|
|
reg = <0xfc428000 0x4000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
tlmm: pinctrl@fd510000 {
|
||
|
|
compatible = "qcom,apq8084-pinctrl";
|
||
|
|
reg = <0xfd510000 0x4000>;
|
||
|
|
gpio-controller;
|
||
|
|
gpio-ranges = <&tlmm 0 0 147>;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp2_uart2: serial@f995e000 {
|
||
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||
|
|
reg = <0xf995e000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
|
||
|
|
clock-names = "core", "iface";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhc_1: mmc@f9824900 {
|
||
|
|
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
|
||
|
|
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
|
||
|
|
reg-names = "hc", "core";
|
||
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
||
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
||
|
|
<&gcc GCC_SDCC1_APPS_CLK>,
|
||
|
|
<&xo_board>;
|
||
|
|
clock-names = "iface", "core", "xo";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhc_2: mmc@f98a4900 {
|
||
|
|
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
|
||
|
|
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
|
||
|
|
reg-names = "hc", "core";
|
||
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
||
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
||
|
|
<&gcc GCC_SDCC2_APPS_CLK>,
|
||
|
|
<&xo_board>;
|
||
|
|
clock-names = "iface", "core", "xo";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spmi_bus: spmi@fc4cf000 {
|
||
|
|
compatible = "qcom,spmi-pmic-arb";
|
||
|
|
reg-names = "core", "intr", "cnfg";
|
||
|
|
reg = <0xfc4cf000 0x1000>,
|
||
|
|
<0xfc4cb000 0x1000>,
|
||
|
|
<0xfc4ca000 0x1000>;
|
||
|
|
interrupt-names = "periph_irq";
|
||
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
qcom,ee = <0>;
|
||
|
|
qcom,channel = <0>;
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <4>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
smd {
|
||
|
|
compatible = "qcom,smd";
|
||
|
|
|
||
|
|
rpm {
|
||
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
||
|
|
qcom,ipc = <&apcs 8 0>;
|
||
|
|
qcom,smd-edge = <15>;
|
||
|
|
|
||
|
|
rpm-requests {
|
||
|
|
compatible = "qcom,rpm-apq8084";
|
||
|
|
qcom,smd-channels = "rpm_requests";
|
||
|
|
|
||
|
|
pma8084-regulators {
|
||
|
|
compatible = "qcom,rpm-pma8084-regulators";
|
||
|
|
|
||
|
|
pma8084_s1: s1 {};
|
||
|
|
pma8084_s2: s2 {};
|
||
|
|
pma8084_s3: s3 {};
|
||
|
|
pma8084_s4: s4 {};
|
||
|
|
pma8084_s5: s5 {};
|
||
|
|
pma8084_s6: s6 {};
|
||
|
|
pma8084_s7: s7 {};
|
||
|
|
pma8084_s8: s8 {};
|
||
|
|
pma8084_s9: s9 {};
|
||
|
|
pma8084_s10: s10 {};
|
||
|
|
pma8084_s11: s11 {};
|
||
|
|
pma8084_s12: s12 {};
|
||
|
|
|
||
|
|
pma8084_l1: l1 {};
|
||
|
|
pma8084_l2: l2 {};
|
||
|
|
pma8084_l3: l3 {};
|
||
|
|
pma8084_l4: l4 {};
|
||
|
|
pma8084_l5: l5 {};
|
||
|
|
pma8084_l6: l6 {};
|
||
|
|
pma8084_l7: l7 {};
|
||
|
|
pma8084_l8: l8 {};
|
||
|
|
pma8084_l9: l9 {};
|
||
|
|
pma8084_l10: l10 {};
|
||
|
|
pma8084_l11: l11 {};
|
||
|
|
pma8084_l12: l12 {};
|
||
|
|
pma8084_l13: l13 {};
|
||
|
|
pma8084_l14: l14 {};
|
||
|
|
pma8084_l15: l15 {};
|
||
|
|
pma8084_l16: l16 {};
|
||
|
|
pma8084_l17: l17 {};
|
||
|
|
pma8084_l18: l18 {};
|
||
|
|
pma8084_l19: l19 {};
|
||
|
|
pma8084_l20: l20 {};
|
||
|
|
pma8084_l21: l21 {};
|
||
|
|
pma8084_l22: l22 {};
|
||
|
|
pma8084_l23: l23 {};
|
||
|
|
pma8084_l24: l24 {};
|
||
|
|
pma8084_l25: l25 {};
|
||
|
|
pma8084_l26: l26 {};
|
||
|
|
pma8084_l27: l27 {};
|
||
|
|
|
||
|
|
pma8084_lvs1: lvs1 {};
|
||
|
|
pma8084_lvs2: lvs2 {};
|
||
|
|
pma8084_lvs3: lvs3 {};
|
||
|
|
pma8084_lvs4: lvs4 {};
|
||
|
|
|
||
|
|
pma8084_5vs1: 5vs1 {};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|