119 lines
4.2 KiB
ReStructuredText
119 lines
4.2 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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=======================================
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QLogic QLGE 10Gb Ethernet device driver
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=======================================
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This driver use drgn and devlink for debugging.
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Dump kernel data structures in drgn
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-----------------------------------
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To dump kernel data structures, the following Python script can be used
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in drgn:
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.. code-block:: python
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def align(x, a):
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"""the alignment a should be a power of 2
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"""
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mask = a - 1
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return (x+ mask) & ~mask
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def struct_size(struct_type):
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struct_str = "struct {}".format(struct_type)
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return sizeof(Object(prog, struct_str, address=0x0))
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def netdev_priv(netdevice):
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NETDEV_ALIGN = 32
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return netdevice.value_() + align(struct_size("net_device"), NETDEV_ALIGN)
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name = 'xxx'
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qlge_device = None
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netdevices = prog['init_net'].dev_base_head.address_of_()
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for netdevice in list_for_each_entry("struct net_device", netdevices, "dev_list"):
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if netdevice.name.string_().decode('ascii') == name:
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print(netdevice.name)
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ql_adapter = Object(prog, "struct ql_adapter", address=netdev_priv(qlge_device))
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The struct ql_adapter will be printed in drgn as follows,
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>>> ql_adapter
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(struct ql_adapter){
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.ricb = (struct ricb){
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.base_cq = (u8)0,
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.flags = (u8)120,
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.mask = (__le16)26637,
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.hash_cq_id = (u8 [1024]){ 172, 142, 255, 255 },
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.ipv6_hash_key = (__le32 [10]){},
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.ipv4_hash_key = (__le32 [4]){},
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},
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.flags = (unsigned long)0,
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.wol = (u32)0,
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.nic_stats = (struct nic_stats){
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.tx_pkts = (u64)0,
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.tx_bytes = (u64)0,
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.tx_mcast_pkts = (u64)0,
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.tx_bcast_pkts = (u64)0,
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.tx_ucast_pkts = (u64)0,
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.tx_ctl_pkts = (u64)0,
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.tx_pause_pkts = (u64)0,
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...
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},
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.active_vlans = (unsigned long [64]){
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 52780853100545, 18446744073709551615,
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18446619461681283072, 0, 42949673024, 2147483647,
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},
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.rx_ring = (struct rx_ring [17]){
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{
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.cqicb = (struct cqicb){
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.msix_vect = (u8)0,
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.reserved1 = (u8)0,
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.reserved2 = (u8)0,
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.flags = (u8)0,
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.len = (__le16)0,
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.rid = (__le16)0,
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...
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},
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.cq_base = (void *)0x0,
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.cq_base_dma = (dma_addr_t)0,
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}
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...
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}
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}
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coredump via devlink
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--------------------
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And the coredump obtained via devlink in json format looks like,
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.. code:: shell
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$ devlink health dump show DEVICE reporter coredump -p -j
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{
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"Core Registers": {
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"segment": 1,
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"values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
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},
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"Test Logic Regs": {
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"segment": 2,
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"values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
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},
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"RMII Registers": {
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"segment": 3,
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"values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
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},
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...
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"Sem Registers": {
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"segment": 50,
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"values": [ 0,0,0,0 ]
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}
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}
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When the module parameter qlge_force_coredump is set to be true, the MPI
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RISC reset before coredumping. So coredumping will much longer since
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devlink tool has to wait for 5 secs for the resetting to be
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finished.
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