701 lines
19 KiB
ReStructuredText
701 lines
19 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0+
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==============================================================
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Linux Driver for the Synopsys(R) Ethernet Controllers "stmmac"
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==============================================================
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Authors: Giuseppe Cavallaro <peppe.cavallaro@st.com>,
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Alexandre Torgue <alexandre.torgue@st.com>, Jose Abreu <joabreu@synopsys.com>
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Contents
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========
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- In This Release
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- Feature List
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- Kernel Configuration
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- Command Line Parameters
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- Driver Information and Notes
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- Debug Information
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- Support
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In This Release
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===============
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This file describes the stmmac Linux Driver for all the Synopsys(R) Ethernet
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Controllers.
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Currently, this network device driver is for all STi embedded MAC/GMAC
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(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XILINX XC2V3000
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FF1152AMT0221 D1215994A VIRTEX FPGA board. The Synopsys Ethernet QoS 5.0 IPK
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is also supported.
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DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
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(and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
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(and upper) have been used for developing this driver as well as
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DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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Enterprise MAC - 100G Ethernet MAC.
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This driver supports both the platform bus and PCI.
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This driver includes support for the following Synopsys(R) DesignWare(R)
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Cores Ethernet Controllers and corresponding minimum and maximum versions:
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+-------------------------------+--------------+--------------+--------------+
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| Controller Name | Min. Version | Max. Version | Abbrev. Name |
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+===============================+==============+==============+==============+
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| Ethernet MAC Universal | N/A | 3.73a | GMAC |
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+-------------------------------+--------------+--------------+--------------+
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| Ethernet Quality-of-Service | 4.00a | N/A | GMAC4+ |
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+-------------------------------+--------------+--------------+--------------+
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| XGMAC - 10G Ethernet MAC | 2.10a | N/A | XGMAC2+ |
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+-------------------------------+--------------+--------------+--------------+
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| XLGMAC - 100G Ethernet MAC | 2.00a | N/A | XLGMAC2+ |
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+-------------------------------+--------------+--------------+--------------+
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For questions related to hardware requirements, refer to the documentation
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supplied with your Ethernet adapter. All hardware requirements listed apply
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to use with Linux.
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Feature List
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============
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The following features are available in this driver:
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- GMII/MII/RGMII/SGMII/RMII/XGMII/XLGMII Interface
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- Half-Duplex / Full-Duplex Operation
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- Energy Efficient Ethernet (EEE)
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- IEEE 802.3x PAUSE Packets (Flow Control)
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- RMON/MIB Counters
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- IEEE 1588 Timestamping (PTP)
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- Pulse-Per-Second Output (PPS)
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- MDIO Clause 22 / Clause 45 Interface
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- MAC Loopback
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- ARP Offloading
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- Automatic CRC / PAD Insertion and Checking
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- Checksum Offload for Received and Transmitted Packets
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- Standard or Jumbo Ethernet Packets
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- Source Address Insertion / Replacement
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- VLAN TAG Insertion / Replacement / Deletion / Filtering (HASH and PERFECT)
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- Programmable TX and RX Watchdog and Coalesce Settings
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- Destination Address Filtering (PERFECT)
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- HASH Filtering (Multicast)
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- Layer 3 / Layer 4 Filtering
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- Remote Wake-Up Detection
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- Receive Side Scaling (RSS)
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- Frame Preemption for TX and RX
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- Programmable Burst Length, Threshold, Queue Size
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- Multiple Queues (up to 8)
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- Multiple Scheduling Algorithms (TX: WRR, DWRR, WFQ, SP, CBS, EST, TBS;
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RX: WRR, SP)
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- Flexible RX Parser
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- TCP / UDP Segmentation Offload (TSO, USO)
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- Split Header (SPH)
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- Safety Features (ECC Protection, Data Parity Protection)
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- Selftests using Ethtool
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Kernel Configuration
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====================
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The kernel configuration option is ``CONFIG_STMMAC_ETH``:
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- ``CONFIG_STMMAC_PLATFORM``: is to enable the platform driver.
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- ``CONFIG_STMMAC_PCI``: is to enable the pci driver.
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Command Line Parameters
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=======================
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If the driver is built as a module the following optional parameters are used
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by entering them on the command line with the modprobe command using this
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syntax (e.g. for PCI module)::
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modprobe stmmac_pci [<option>=<VAL1>,<VAL2>,...]
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Driver parameters can be also passed in command line by using::
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stmmaceth=watchdog:100,chain_mode=1
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The default value for each parameter is generally the recommended setting,
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unless otherwise noted.
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watchdog
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--------
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:Valid Range: 5000-None
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:Default Value: 5000
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This parameter overrides the transmit timeout in milliseconds.
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debug
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-----
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:Valid Range: 0-16 (0=none,...,16=all)
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:Default Value: 0
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This parameter adjusts the level of debug messages displayed in the system
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logs.
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phyaddr
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-------
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:Valid Range: 0-31
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:Default Value: -1
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This parameter overrides the physical address of the PHY device.
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flow_ctrl
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---------
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:Valid Range: 0-3 (0=off,1=rx,2=tx,3=rx/tx)
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:Default Value: 3
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This parameter changes the default Flow Control ability.
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pause
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-----
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:Valid Range: 0-65535
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:Default Value: 65535
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This parameter changes the default Flow Control Pause time.
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tc
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--
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:Valid Range: 64-256
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:Default Value: 64
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This parameter changes the default HW FIFO Threshold control value.
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buf_sz
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------
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:Valid Range: 1536-16384
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:Default Value: 1536
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This parameter changes the default RX DMA packet buffer size.
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eee_timer
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---------
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:Valid Range: 0-None
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:Default Value: 1000
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This parameter changes the default LPI TX Expiration time in milliseconds.
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chain_mode
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----------
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:Valid Range: 0-1 (0=off,1=on)
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:Default Value: 0
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This parameter changes the default mode of operation from Ring Mode to
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Chain Mode.
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Driver Information and Notes
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============================
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Transmit Process
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----------------
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The xmit method is invoked when the kernel needs to transmit a packet; it sets
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the descriptors in the ring and informs the DMA engine that there is a packet
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ready to be transmitted.
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By default, the driver sets the ``NETIF_F_SG`` bit in the features field of
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the ``net_device`` structure, enabling the scatter-gather feature. This is
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true on chips and configurations where the checksum can be done in hardware.
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Once the controller has finished transmitting the packet, timer will be
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scheduled to release the transmit resources.
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Receive Process
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---------------
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When one or more packets are received, an interrupt happens. The interrupts
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are not queued, so the driver has to scan all the descriptors in the ring
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during the receive process.
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This is based on NAPI, so the interrupt handler signals only if there is work
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to be done, and it exits. Then the poll method will be scheduled at some
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future point.
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The incoming packets are stored, by the DMA, in a list of pre-allocated socket
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buffers in order to avoid the memcpy (zero-copy).
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Interrupt Mitigation
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--------------------
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The driver is able to mitigate the number of its DMA interrupts using NAPI for
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the reception on chips older than the 3.50. New chips have an HW RX Watchdog
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used for this mitigation.
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Mitigation parameters can be tuned by ethtool.
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WoL
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---
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Wake up on Lan feature through Magic and Unicast frames are supported for the
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GMAC, GMAC4/5 and XGMAC core.
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DMA Descriptors
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---------------
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Driver handles both normal and alternate descriptors. The latter has been only
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tested on DesignWare(R) Cores Ethernet MAC Universal version 3.41a and later.
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stmmac supports DMA descriptor to operate both in dual buffer (RING) and
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linked-list(CHAINED) mode. In RING each descriptor points to two data buffer
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pointers whereas in CHAINED mode they point to only one data buffer pointer.
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RING mode is the default.
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In CHAINED mode each descriptor will have pointer to next descriptor in the
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list, hence creating the explicit chaining in the descriptor itself, whereas
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such explicit chaining is not possible in RING mode.
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Extended Descriptors
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--------------------
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The extended descriptors give us information about the Ethernet payload when
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it is carrying PTP packets or TCP/UDP/ICMP over IP. These are not available on
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GMAC Synopsys(R) chips older than the 3.50. At probe time the driver will
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decide if these can be actually used. This support also is mandatory for PTPv2
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because the extra descriptors are used for saving the hardware timestamps and
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Extended Status.
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Ethtool Support
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---------------
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Ethtool is supported. For example, driver statistics (including RMON),
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internal errors can be taken using::
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ethtool -S ethX
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Ethtool selftests are also supported. This allows to do some early sanity
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checks to the HW using MAC and PHY loopback mechanisms::
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ethtool -t ethX
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Jumbo and Segmentation Offloading
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---------------------------------
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Jumbo frames are supported and tested for the GMAC. The GSO has been also
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added but it's performed in software. LRO is not supported.
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TSO Support
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-----------
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TSO (TCP Segmentation Offload) feature is supported by GMAC > 4.x and XGMAC
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chip family. When a packet is sent through TCP protocol, the TCP stack ensures
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that the SKB provided to the low level driver (stmmac in our case) matches
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with the maximum frame len (IP header + TCP header + payload <= 1500 bytes
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(for MTU set to 1500)). It means that if an application using TCP want to send
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a packet which will have a length (after adding headers) > 1514 the packet
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will be split in several TCP packets: The data payload is split and headers
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(TCP/IP ..) are added. It is done by software.
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When TSO is enabled, the TCP stack doesn't care about the maximum frame length
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and provide SKB packet to stmmac as it is. The GMAC IP will have to perform
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the segmentation by it self to match with maximum frame length.
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This feature can be enabled in device tree through ``snps,tso`` entry.
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Energy Efficient Ethernet
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-------------------------
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Energy Efficient Ethernet (EEE) enables IEEE 802.3 MAC sublayer along with a
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family of Physical layer to operate in the Low Power Idle (LPI) mode. The EEE
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mode supports the IEEE 802.3 MAC operation at 100Mbps, 1000Mbps and 1Gbps.
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The LPI mode allows power saving by switching off parts of the communication
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device functionality when there is no data to be transmitted & received.
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The system on both the side of the link can disable some functionalities and
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save power during the period of low-link utilization. The MAC controls whether
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the system should enter or exit the LPI mode and communicate this to PHY.
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As soon as the interface is opened, the driver verifies if the EEE can be
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supported. This is done by looking at both the DMA HW capability register and
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the PHY devices MCD registers.
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To enter in TX LPI mode the driver needs to have a software timer that enable
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and disable the LPI mode when there is nothing to be transmitted.
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Precision Time Protocol (PTP)
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-----------------------------
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The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP), which
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enables precise synchronization of clocks in measurement and control systems
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implemented with technologies such as network communication.
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In addition to the basic timestamp features mentioned in IEEE 1588-2002
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Timestamps, new GMAC cores support the advanced timestamp features.
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IEEE 1588-2008 can be enabled when configuring the Kernel.
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SGMII/RGMII Support
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-------------------
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New GMAC devices provide own way to manage RGMII/SGMII. This information is
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available at run-time by looking at the HW capability register. This means
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that the stmmac can manage auto-negotiation and link status w/o using the
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PHYLIB stuff. In fact, the HW provides a subset of extended registers to
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restart the ANE, verify Full/Half duplex mode and Speed. Thanks to these
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registers, it is possible to look at the Auto-negotiated Link Parter Ability.
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Physical
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--------
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The driver is compatible with Physical Abstraction Layer to be connected with
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PHY and GPHY devices.
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Platform Information
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--------------------
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Several information can be passed through the platform and device-tree.
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::
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struct plat_stmmacenet_data {
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1) Bus identifier::
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int bus_id;
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2) PHY Physical Address. If set to -1 the driver will pick the first PHY it
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finds::
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int phy_addr;
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3) PHY Device Interface::
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int interface;
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4) Specific platform fields for the MDIO bus::
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struct stmmac_mdio_bus_data *mdio_bus_data;
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5) Internal DMA parameters::
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struct stmmac_dma_cfg *dma_cfg;
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6) Fixed CSR Clock Range selection::
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int clk_csr;
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7) HW uses the GMAC core::
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int has_gmac;
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8) If set the MAC will use Enhanced Descriptors::
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int enh_desc;
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9) Core is able to perform TX Checksum and/or RX Checksum in HW::
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int tx_coe;
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int rx_coe;
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11) Some HWs are not able to perform the csum in HW for over-sized frames due
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to limited buffer sizes. Setting this flag the csum will be done in SW on
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JUMBO frames::
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int bugged_jumbo;
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12) Core has the embedded power module::
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int pmt;
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13) Force DMA to use the Store and Forward mode or Threshold mode::
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int force_sf_dma_mode;
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int force_thresh_dma_mode;
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15) Force to disable the RX Watchdog feature and switch to NAPI mode::
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int riwt_off;
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16) Limit the maximum operating speed and MTU::
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int max_speed;
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int maxmtu;
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18) Number of Multicast/Unicast filters::
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int multicast_filter_bins;
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int unicast_filter_entries;
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20) Limit the maximum TX and RX FIFO size::
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int tx_fifo_size;
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int rx_fifo_size;
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21) Use the specified number of TX and RX Queues::
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u32 rx_queues_to_use;
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u32 tx_queues_to_use;
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22) Use the specified TX and RX scheduling algorithm::
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u8 rx_sched_algorithm;
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u8 tx_sched_algorithm;
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23) Internal TX and RX Queue parameters::
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struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
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struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
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24) This callback is used for modifying some syscfg registers (on ST SoCs)
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according to the link speed negotiated by the physical layer::
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void (*fix_mac_speed)(void *priv, unsigned int speed);
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25) Callbacks used for calling a custom initialization; This is sometimes
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necessary on some platforms (e.g. ST boxes) where the HW needs to have set
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some PIO lines or system cfg registers. init/exit callbacks should not use
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or modify platform data::
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int (*init)(struct platform_device *pdev, void *priv);
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void (*exit)(struct platform_device *pdev, void *priv);
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26) Perform HW setup of the bus. For example, on some ST platforms this field
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is used to configure the AMBA bridge to generate more efficient STBus traffic::
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struct mac_device_info *(*setup)(void *priv);
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void *bsp_priv;
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27) Internal clocks and rates::
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struct clk *stmmac_clk;
|
||
|
struct clk *pclk;
|
||
|
struct clk *clk_ptp_ref;
|
||
|
unsigned int clk_ptp_rate;
|
||
|
unsigned int clk_ref_rate;
|
||
|
s32 ptp_max_adj;
|
||
|
|
||
|
28) Main reset::
|
||
|
|
||
|
struct reset_control *stmmac_rst;
|
||
|
|
||
|
29) AXI Internal Parameters::
|
||
|
|
||
|
struct stmmac_axi *axi;
|
||
|
|
||
|
30) HW uses GMAC>4 cores::
|
||
|
|
||
|
int has_gmac4;
|
||
|
|
||
|
31) HW is sun8i based::
|
||
|
|
||
|
bool has_sun8i;
|
||
|
|
||
|
32) Enables TSO feature::
|
||
|
|
||
|
bool tso_en;
|
||
|
|
||
|
33) Enables Receive Side Scaling (RSS) feature::
|
||
|
|
||
|
int rss_en;
|
||
|
|
||
|
34) MAC Port selection::
|
||
|
|
||
|
int mac_port_sel_speed;
|
||
|
|
||
|
35) Enables TX LPI Clock Gating::
|
||
|
|
||
|
bool en_tx_lpi_clockgating;
|
||
|
|
||
|
36) HW uses XGMAC>2.10 cores::
|
||
|
|
||
|
int has_xgmac;
|
||
|
|
||
|
::
|
||
|
|
||
|
}
|
||
|
|
||
|
For MDIO bus data, we have:
|
||
|
|
||
|
::
|
||
|
|
||
|
struct stmmac_mdio_bus_data {
|
||
|
|
||
|
1) PHY mask passed when MDIO bus is registered::
|
||
|
|
||
|
unsigned int phy_mask;
|
||
|
|
||
|
2) List of IRQs, one per PHY::
|
||
|
|
||
|
int *irqs;
|
||
|
|
||
|
3) If IRQs is NULL, use this for probed PHY::
|
||
|
|
||
|
int probed_phy_irq;
|
||
|
|
||
|
4) Set to true if PHY needs reset::
|
||
|
|
||
|
bool needs_reset;
|
||
|
|
||
|
::
|
||
|
|
||
|
}
|
||
|
|
||
|
For DMA engine configuration, we have:
|
||
|
|
||
|
::
|
||
|
|
||
|
struct stmmac_dma_cfg {
|
||
|
|
||
|
1) Programmable Burst Length (TX and RX)::
|
||
|
|
||
|
int pbl;
|
||
|
|
||
|
2) If set, DMA TX / RX will use this value rather than pbl::
|
||
|
|
||
|
int txpbl;
|
||
|
int rxpbl;
|
||
|
|
||
|
3) Enable 8xPBL::
|
||
|
|
||
|
bool pblx8;
|
||
|
|
||
|
4) Enable Fixed or Mixed burst::
|
||
|
|
||
|
int fixed_burst;
|
||
|
int mixed_burst;
|
||
|
|
||
|
5) Enable Address Aligned Beats::
|
||
|
|
||
|
bool aal;
|
||
|
|
||
|
6) Enable Enhanced Addressing (> 32 bits)::
|
||
|
|
||
|
bool eame;
|
||
|
|
||
|
::
|
||
|
|
||
|
}
|
||
|
|
||
|
For DMA AXI parameters, we have:
|
||
|
|
||
|
::
|
||
|
|
||
|
struct stmmac_axi {
|
||
|
|
||
|
1) Enable AXI LPI::
|
||
|
|
||
|
bool axi_lpi_en;
|
||
|
bool axi_xit_frm;
|
||
|
|
||
|
2) Set AXI Write / Read maximum outstanding requests::
|
||
|
|
||
|
u32 axi_wr_osr_lmt;
|
||
|
u32 axi_rd_osr_lmt;
|
||
|
|
||
|
3) Set AXI 4KB bursts::
|
||
|
|
||
|
bool axi_kbbe;
|
||
|
|
||
|
4) Set AXI maximum burst length map::
|
||
|
|
||
|
u32 axi_blen[AXI_BLEN];
|
||
|
|
||
|
5) Set AXI Fixed burst / mixed burst::
|
||
|
|
||
|
bool axi_fb;
|
||
|
bool axi_mb;
|
||
|
|
||
|
6) Set AXI rebuild incrx mode::
|
||
|
|
||
|
bool axi_rb;
|
||
|
|
||
|
::
|
||
|
|
||
|
}
|
||
|
|
||
|
For the RX Queues configuration, we have:
|
||
|
|
||
|
::
|
||
|
|
||
|
struct stmmac_rxq_cfg {
|
||
|
|
||
|
1) Mode to use (DCB or AVB)::
|
||
|
|
||
|
u8 mode_to_use;
|
||
|
|
||
|
2) DMA channel to use::
|
||
|
|
||
|
u32 chan;
|
||
|
|
||
|
3) Packet routing, if applicable::
|
||
|
|
||
|
u8 pkt_route;
|
||
|
|
||
|
4) Use priority routing, and priority to route::
|
||
|
|
||
|
bool use_prio;
|
||
|
u32 prio;
|
||
|
|
||
|
::
|
||
|
|
||
|
}
|
||
|
|
||
|
For the TX Queues configuration, we have:
|
||
|
|
||
|
::
|
||
|
|
||
|
struct stmmac_txq_cfg {
|
||
|
|
||
|
1) Queue weight in scheduler::
|
||
|
|
||
|
u32 weight;
|
||
|
|
||
|
2) Mode to use (DCB or AVB)::
|
||
|
|
||
|
u8 mode_to_use;
|
||
|
|
||
|
3) Credit Base Shaper Parameters::
|
||
|
|
||
|
u32 send_slope;
|
||
|
u32 idle_slope;
|
||
|
u32 high_credit;
|
||
|
u32 low_credit;
|
||
|
|
||
|
4) Use priority scheduling, and priority::
|
||
|
|
||
|
bool use_prio;
|
||
|
u32 prio;
|
||
|
|
||
|
::
|
||
|
|
||
|
}
|
||
|
|
||
|
Device Tree Information
|
||
|
-----------------------
|
||
|
|
||
|
Please refer to the following document:
|
||
|
Documentation/devicetree/bindings/net/snps,dwmac.yaml
|
||
|
|
||
|
HW Capabilities
|
||
|
---------------
|
||
|
|
||
|
Note that, starting from new chips, where it is available the HW capability
|
||
|
register, many configurations are discovered at run-time for example to
|
||
|
understand if EEE, HW csum, PTP, enhanced descriptor etc are actually
|
||
|
available. As strategy adopted in this driver, the information from the HW
|
||
|
capability register can replace what has been passed from the platform.
|
||
|
|
||
|
Debug Information
|
||
|
=================
|
||
|
|
||
|
The driver exports many information i.e. internal statistics, debug
|
||
|
information, MAC and DMA registers etc.
|
||
|
|
||
|
These can be read in several ways depending on the type of the information
|
||
|
actually needed.
|
||
|
|
||
|
For example a user can be use the ethtool support to get statistics: e.g.
|
||
|
using: ``ethtool -S ethX`` (that shows the Management counters (MMC) if
|
||
|
supported) or sees the MAC/DMA registers: e.g. using: ``ethtool -d ethX``
|
||
|
|
||
|
Compiling the Kernel with ``CONFIG_DEBUG_FS`` the driver will export the
|
||
|
following debugfs entries:
|
||
|
|
||
|
- ``descriptors_status``: To show the DMA TX/RX descriptor rings
|
||
|
- ``dma_cap``: To show the HW Capabilities
|
||
|
|
||
|
Developer can also use the ``debug`` module parameter to get further debug
|
||
|
information (please see: NETIF Msg Level).
|
||
|
|
||
|
Support
|
||
|
=======
|
||
|
|
||
|
If an issue is identified with the released source code on a supported kernel
|
||
|
with a supported adapter, email the specific information related to the
|
||
|
issue to netdev@vger.kernel.org
|