413 lines
16 KiB
ReStructuredText
413 lines
16 KiB
ReStructuredText
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I2C muxes and complex topologies
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================================
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There are a couple of reasons for building more complex I2C topologies
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than a straight-forward I2C bus with one adapter and one or more devices.
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Some example use cases are:
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1. A mux may be needed on the bus to prevent address collisions.
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2. The bus may be accessible from some external bus master, and arbitration
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may be needed to determine if it is ok to access the bus.
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3. A device (particularly RF tuners) may want to avoid the digital noise
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from the I2C bus, at least most of the time, and sits behind a gate
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that has to be operated before the device can be accessed.
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Several types of hardware components such as I2C muxes, I2C gates and I2C
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arbitrators allow to handle such needs.
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These components are represented as I2C adapter trees by Linux, where
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each adapter has a parent adapter (except the root adapter) and zero or
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more child adapters. The root adapter is the actual adapter that issues
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I2C transfers, and all adapters with a parent are part of an "i2c-mux"
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object (quoted, since it can also be an arbitrator or a gate).
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Depending of the particular mux driver, something happens when there is
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an I2C transfer on one of its child adapters. The mux driver can
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obviously operate a mux, but it can also do arbitration with an external
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bus master or open a gate. The mux driver has two operations for this,
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select and deselect. select is called before the transfer and (the
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optional) deselect is called after the transfer.
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Locking
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=======
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There are two variants of locking available to I2C muxes, they can be
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mux-locked or parent-locked muxes.
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Mux-locked muxes
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----------------
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Mux-locked muxes does not lock the entire parent adapter during the
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full select-transfer-deselect transaction, only the muxes on the parent
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adapter are locked. Mux-locked muxes are mostly interesting if the
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select and/or deselect operations must use I2C transfers to complete
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their tasks. Since the parent adapter is not fully locked during the
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full transaction, unrelated I2C transfers may interleave the different
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stages of the transaction. This has the benefit that the mux driver
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may be easier and cleaner to implement, but it has some caveats.
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Mux-locked Example
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~~~~~~~~~~~~~~~~~~
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::
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.----------. .--------.
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.--------. | mux- |-----| dev D1 |
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| root |--+--| locked | '--------'
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'--------' | | mux M1 |--. .--------.
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| '----------' '--| dev D2 |
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| .--------. '--------'
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'--| dev D3 |
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'--------'
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When there is an access to D1, this happens:
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1. Someone issues an I2C transfer to D1.
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2. M1 locks muxes on its parent (the root adapter in this case).
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3. M1 calls ->select to ready the mux.
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4. M1 (presumably) does some I2C transfers as part of its select.
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These transfers are normal I2C transfers that locks the parent
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adapter.
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5. M1 feeds the I2C transfer from step 1 to its parent adapter as a
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normal I2C transfer that locks the parent adapter.
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6. M1 calls ->deselect, if it has one.
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7. Same rules as in step 4, but for ->deselect.
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8. M1 unlocks muxes on its parent.
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This means that accesses to D2 are lockout out for the full duration
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of the entire operation. But accesses to D3 are possibly interleaved
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at any point.
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Mux-locked caveats
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~~~~~~~~~~~~~~~~~~
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When using a mux-locked mux, be aware of the following restrictions:
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[ML1]
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If you build a topology with a mux-locked mux being the parent
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of a parent-locked mux, this might break the expectation from the
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parent-locked mux that the root adapter is locked during the
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transaction.
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[ML2]
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It is not safe to build arbitrary topologies with two (or more)
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mux-locked muxes that are not siblings, when there are address
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collisions between the devices on the child adapters of these
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non-sibling muxes.
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I.e. the select-transfer-deselect transaction targeting e.g. device
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address 0x42 behind mux-one may be interleaved with a similar
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operation targeting device address 0x42 behind mux-two. The
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intent with such a topology would in this hypothetical example
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be that mux-one and mux-two should not be selected simultaneously,
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but mux-locked muxes do not guarantee that in all topologies.
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[ML3]
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A mux-locked mux cannot be used by a driver for auto-closing
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gates/muxes, i.e. something that closes automatically after a given
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number (one, in most cases) of I2C transfers. Unrelated I2C transfers
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may creep in and close prematurely.
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[ML4]
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If any non-I2C operation in the mux driver changes the I2C mux state,
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the driver has to lock the root adapter during that operation.
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Otherwise garbage may appear on the bus as seen from devices
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behind the mux, when an unrelated I2C transfer is in flight during
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the non-I2C mux-changing operation.
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Parent-locked muxes
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-------------------
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Parent-locked muxes lock the parent adapter during the full select-
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transfer-deselect transaction. The implication is that the mux driver
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has to ensure that any and all I2C transfers through that parent
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adapter during the transaction are unlocked I2C transfers (using e.g.
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__i2c_transfer), or a deadlock will follow.
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Parent-locked Example
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~~~~~~~~~~~~~~~~~~~~~
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::
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.----------. .--------.
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.--------. | parent- |-----| dev D1 |
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| root |--+--| locked | '--------'
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'--------' | | mux M1 |--. .--------.
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| '----------' '--| dev D2 |
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| .--------. '--------'
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'--| dev D3 |
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'--------'
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When there is an access to D1, this happens:
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1. Someone issues an I2C transfer to D1.
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2. M1 locks muxes on its parent (the root adapter in this case).
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3. M1 locks its parent adapter.
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4. M1 calls ->select to ready the mux.
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5. If M1 does any I2C transfers (on this root adapter) as part of
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its select, those transfers must be unlocked I2C transfers so
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that they do not deadlock the root adapter.
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6. M1 feeds the I2C transfer from step 1 to the root adapter as an
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unlocked I2C transfer, so that it does not deadlock the parent
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adapter.
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7. M1 calls ->deselect, if it has one.
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8. Same rules as in step 5, but for ->deselect.
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9. M1 unlocks its parent adapter.
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10. M1 unlocks muxes on its parent.
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This means that accesses to both D2 and D3 are locked out for the full
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duration of the entire operation.
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Parent-locked Caveats
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~~~~~~~~~~~~~~~~~~~~~
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When using a parent-locked mux, be aware of the following restrictions:
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[PL1]
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If you build a topology with a parent-locked mux being the child
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of another mux, this might break a possible assumption from the
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child mux that the root adapter is unused between its select op
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and the actual transfer (e.g. if the child mux is auto-closing
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and the parent mux issues I2C transfers as part of its select).
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This is especially the case if the parent mux is mux-locked, but
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it may also happen if the parent mux is parent-locked.
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[PL2]
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If select/deselect calls out to other subsystems such as gpio,
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pinctrl, regmap or iio, it is essential that any I2C transfers
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caused by these subsystems are unlocked. This can be convoluted to
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accomplish, maybe even impossible if an acceptably clean solution
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is sought.
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Complex Examples
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================
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Parent-locked mux as parent of parent-locked mux
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------------------------------------------------
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This is a useful topology, but it can be bad::
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.----------. .----------. .--------.
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.--------. | parent- |-----| parent- |-----| dev D1 |
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| root |--+--| locked | | locked | '--------'
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'--------' | | mux M1 |--. | mux M2 |--. .--------.
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| '----------' | '----------' '--| dev D2 |
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| .--------. | .--------. '--------'
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'--| dev D4 | '--| dev D3 |
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'--------' '--------'
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When any device is accessed, all other devices are locked out for
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the full duration of the operation (both muxes lock their parent,
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and specifically when M2 requests its parent to lock, M1 passes
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the buck to the root adapter).
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This topology is bad if M2 is an auto-closing mux and M1->select
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issues any unlocked I2C transfers on the root adapter that may leak
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through and be seen by the M2 adapter, thus closing M2 prematurely.
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Mux-locked mux as parent of mux-locked mux
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------------------------------------------
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This is a good topology::
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.----------. .----------. .--------.
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.--------. | mux- |-----| mux- |-----| dev D1 |
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| root |--+--| locked | | locked | '--------'
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'--------' | | mux M1 |--. | mux M2 |--. .--------.
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| '----------' | '----------' '--| dev D2 |
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| .--------. | .--------. '--------'
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'--| dev D4 | '--| dev D3 |
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'--------' '--------'
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When device D1 is accessed, accesses to D2 are locked out for the
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full duration of the operation (muxes on the top child adapter of M1
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are locked). But accesses to D3 and D4 are possibly interleaved at
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any point.
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Accesses to D3 locks out D1 and D2, but accesses to D4 are still possibly
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interleaved.
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Mux-locked mux as parent of parent-locked mux
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---------------------------------------------
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This is probably a bad topology::
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.----------. .----------. .--------.
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.--------. | mux- |-----| parent- |-----| dev D1 |
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| root |--+--| locked | | locked | '--------'
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'--------' | | mux M1 |--. | mux M2 |--. .--------.
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| '----------' | '----------' '--| dev D2 |
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| .--------. | .--------. '--------'
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'--| dev D4 | '--| dev D3 |
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'--------' '--------'
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When device D1 is accessed, accesses to D2 and D3 are locked out
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for the full duration of the operation (M1 locks child muxes on the
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root adapter). But accesses to D4 are possibly interleaved at any
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point.
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This kind of topology is generally not suitable and should probably
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be avoided. The reason is that M2 probably assumes that there will
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be no I2C transfers during its calls to ->select and ->deselect, and
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if there are, any such transfers might appear on the slave side of M2
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as partial I2C transfers, i.e. garbage or worse. This might cause
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device lockups and/or other problems.
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The topology is especially troublesome if M2 is an auto-closing
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mux. In that case, any interleaved accesses to D4 might close M2
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prematurely, as might any I2C transfers part of M1->select.
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But if M2 is not making the above stated assumption, and if M2 is not
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auto-closing, the topology is fine.
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Parent-locked mux as parent of mux-locked mux
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---------------------------------------------
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This is a good topology::
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.----------. .----------. .--------.
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.--------. | parent- |-----| mux- |-----| dev D1 |
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| root |--+--| locked | | locked | '--------'
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'--------' | | mux M1 |--. | mux M2 |--. .--------.
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| '----------' | '----------' '--| dev D2 |
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| .--------. | .--------. '--------'
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'--| dev D4 | '--| dev D3 |
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'--------' '--------'
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When D1 is accessed, accesses to D2 are locked out for the full
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duration of the operation (muxes on the top child adapter of M1
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are locked). Accesses to D3 and D4 are possibly interleaved at
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any point, just as is expected for mux-locked muxes.
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When D3 or D4 are accessed, everything else is locked out. For D3
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accesses, M1 locks the root adapter. For D4 accesses, the root
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adapter is locked directly.
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Two mux-locked sibling muxes
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----------------------------
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This is a good topology::
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.--------.
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.----------. .--| dev D1 |
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| mux- |--' '--------'
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.--| locked | .--------.
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| | mux M1 |-----| dev D2 |
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| '----------' '--------'
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| .----------. .--------.
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.--------. | | mux- |-----| dev D3 |
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| root |--+--| locked | '--------'
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'--------' | | mux M2 |--. .--------.
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| '----------' '--| dev D4 |
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| .--------. '--------'
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'--| dev D5 |
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'--------'
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When D1 is accessed, accesses to D2, D3 and D4 are locked out. But
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accesses to D5 may be interleaved at any time.
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Two parent-locked sibling muxes
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-------------------------------
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This is a good topology::
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.--------.
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.----------. .--| dev D1 |
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| parent- |--' '--------'
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.--| locked | .--------.
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| | mux M1 |-----| dev D2 |
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| '----------' '--------'
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| .----------. .--------.
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.--------. | | parent- |-----| dev D3 |
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| root |--+--| locked | '--------'
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'--------' | | mux M2 |--. .--------.
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| '----------' '--| dev D4 |
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| .--------. '--------'
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'--| dev D5 |
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'--------'
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When any device is accessed, accesses to all other devices are locked
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out.
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Mux-locked and parent-locked sibling muxes
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------------------------------------------
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This is a good topology::
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.--------.
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.----------. .--| dev D1 |
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| mux- |--' '--------'
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.--| locked | .--------.
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| | mux M1 |-----| dev D2 |
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| '----------' '--------'
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| .----------. .--------.
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.--------. | | parent- |-----| dev D3 |
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| root |--+--| locked | '--------'
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'--------' | | mux M2 |--. .--------.
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| '----------' '--| dev D4 |
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| .--------. '--------'
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'--| dev D5 |
|
||
|
|
'--------'
|
||
|
|
|
||
|
|
When D1 or D2 are accessed, accesses to D3 and D4 are locked out while
|
||
|
|
accesses to D5 may interleave. When D3 or D4 are accessed, accesses to
|
||
|
|
all other devices are locked out.
|
||
|
|
|
||
|
|
|
||
|
|
Mux type of existing device drivers
|
||
|
|
===================================
|
||
|
|
|
||
|
|
Whether a device is mux-locked or parent-locked depends on its
|
||
|
|
implementation. The following list was correct at the time of writing:
|
||
|
|
|
||
|
|
In drivers/i2c/muxes/:
|
||
|
|
|
||
|
|
====================== =============================================
|
||
|
|
i2c-arb-gpio-challenge Parent-locked
|
||
|
|
i2c-mux-gpio Normally parent-locked, mux-locked iff
|
||
|
|
all involved gpio pins are controlled by the
|
||
|
|
same I2C root adapter that they mux.
|
||
|
|
i2c-mux-gpmux Normally parent-locked, mux-locked iff
|
||
|
|
specified in device-tree.
|
||
|
|
i2c-mux-ltc4306 Mux-locked
|
||
|
|
i2c-mux-mlxcpld Parent-locked
|
||
|
|
i2c-mux-pca9541 Parent-locked
|
||
|
|
i2c-mux-pca954x Parent-locked
|
||
|
|
i2c-mux-pinctrl Normally parent-locked, mux-locked iff
|
||
|
|
all involved pinctrl devices are controlled
|
||
|
|
by the same I2C root adapter that they mux.
|
||
|
|
i2c-mux-reg Parent-locked
|
||
|
|
====================== =============================================
|
||
|
|
|
||
|
|
In drivers/iio/:
|
||
|
|
|
||
|
|
====================== =============================================
|
||
|
|
gyro/mpu3050 Mux-locked
|
||
|
|
imu/inv_mpu6050/ Mux-locked
|
||
|
|
====================== =============================================
|
||
|
|
|
||
|
|
In drivers/media/:
|
||
|
|
|
||
|
|
======================= =============================================
|
||
|
|
dvb-frontends/lgdt3306a Mux-locked
|
||
|
|
dvb-frontends/m88ds3103 Parent-locked
|
||
|
|
dvb-frontends/rtl2830 Parent-locked
|
||
|
|
dvb-frontends/rtl2832 Mux-locked
|
||
|
|
dvb-frontends/si2168 Mux-locked
|
||
|
|
usb/cx231xx/ Parent-locked
|
||
|
|
======================= =============================================
|