88 lines
2.1 KiB
YAML
88 lines
2.1 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive SPI controller
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maintainers:
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- Pragnesh Patel <pragnesh.patel@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Palmer Dabbelt <palmer@sifive.com>
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allOf:
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- $ref: "spi-controller.yaml#"
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properties:
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compatible:
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items:
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- enum:
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- sifive,fu540-c000-spi
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- sifive,fu740-c000-spi
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- const: sifive,spi0
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description:
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Should be "sifive,<chip>-spi" and "sifive,spi<version>".
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Supported compatible strings are -
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"sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
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as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
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for the SiFive SPI v0 IP block with no chip integration tweaks.
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Please refer to sifive-blocks-ip-versioning.txt for details
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SPI RTL that corresponds to the IP block version numbers can be found here -
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
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reg:
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minItems: 1
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items:
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- description: SPI registers region
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- description: Memory mapped flash region
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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description:
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Must reference the frequency given to the controller
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sifive,fifo-depth:
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description:
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Depth of hardware queues; defaults to 8
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum: [8]
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default: 8
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sifive,max-bits-per-word:
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description:
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Maximum bits per word; defaults to 8
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
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default: 8
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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spi: spi@10040000 {
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compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
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interrupt-parent = <&plic>;
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interrupts = <51>;
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clocks = <&tlclk>;
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#address-cells = <1>;
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#size-cells = <0>;
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sifive,fifo-depth = <8>;
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sifive,max-bits-per-word = <8>;
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};
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...
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