314 lines
11 KiB
YAML
314 lines
11 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI K3 R5F processor subsystems
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maintainers:
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- Suman Anna <s-anna@ti.com>
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description: |
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The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
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processor subsystems/clusters (R5FSS). The dual core cluster can be used
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either in a LockStep mode providing safety/fault tolerance features or in a
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Split mode providing two individual compute cores for doubling the compute
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capacity on most SoCs. These are used together with other processors present
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on the SoC to achieve various system level goals.
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AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
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called "Single-CPU" mode, where only Core0 is used, but with ability to use
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Core1's TCMs as well.
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Each Dual-Core R5F sub-system is represented as a single DTS node
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representing the cluster, with a pair of child DT nodes representing
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the individual R5F cores. Each node has a number of required or optional
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properties that enable the OS running on the host processor to perform
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the device management of the remote processor and to communicate with the
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remote processor.
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properties:
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$nodename:
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pattern: "^r5fss(@.*)?"
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compatible:
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enum:
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- ti,am654-r5fss
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- ti,j721e-r5fss
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- ti,j7200-r5fss
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- ti,am64-r5fss
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- ti,j721s2-r5fss
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power-domains:
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description: |
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Should contain a phandle to a PM domain provider node and an args
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specifier containing the R5FSS device id value.
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges:
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description: |
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Standard ranges definition providing address translations for
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local R5F TCM address spaces to bus addresses.
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# Optional properties:
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# --------------------
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ti,cluster-mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Configuration Mode for the Dual R5F cores within the R5F cluster.
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Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
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most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if
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omitted; and should be either a value of 0 (Split mode) or 2
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(Single-CPU mode) on AM64x SoCs, default is Split mode if omitted.
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# R5F Processor Child Nodes:
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# ==========================
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patternProperties:
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"^r5f@[a-f0-9]+$":
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type: object
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description: |
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The R5F Sub-System device node should define two R5F child nodes, each
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node representing a TI instantiation of the Arm Cortex R5F core. There
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are some specific integration differences for the IP like the usage of
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a Region Address Translator (RAT) for translating the larger SoC bus
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addresses into a 32-bit address space for the processor.
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Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
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internal memories split between two banks - TCMA and TCMB (further
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interleaved into two banks TCMB0 and TCMB1). These memories (also called
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ATCM and BTCM) provide read/write performance on par with the core's L1
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caches. Each of the TCMs can be enabled or disabled independently and
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either of them can be configured to appear at that R5F's address 0x0.
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The cores do not use an MMU, but has a Region Address Translater
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(RAT) module that is accessible only from the R5Fs for providing
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translations between 32-bit CPU addresses into larger system bus
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addresses. Cache and memory access settings are provided through a
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Memory Protection Unit (MPU), programmable only from the R5Fs.
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$ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
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properties:
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compatible:
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enum:
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- ti,am654-r5f
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- ti,j721e-r5f
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- ti,j7200-r5f
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- ti,am64-r5f
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- ti,j721s2-r5f
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reg:
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items:
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- description: Address and Size of the ATCM internal memory region
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- description: Address and Size of the BTCM internal memory region
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reg-names:
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items:
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- const: atcm
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- const: btcm
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resets:
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description: |
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Should contain the phandle to the reset controller node managing the
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local resets for this device, and a reset specifier.
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maxItems: 1
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firmware-name:
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description: |
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Should contain the name of the default firmware image
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file located on the firmware search path
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# The following properties are mandatory for R5F Core0 in both LockStep and Split
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# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
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# R5F Core1 in LockStep mode:
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mboxes:
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description: |
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OMAP Mailbox specifier denoting the sub-mailbox, to be used for
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communication with the remote processor. This property should match
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with the sub-mailbox node used in the firmware image.
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maxItems: 1
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memory-region:
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description: |
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phandle to the reserved memory nodes to be associated with the
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remoteproc device. There should be at least two reserved memory nodes
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defined. The reserved memory nodes should be carveout nodes, and
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should be defined with a "no-map" property as per the bindings in
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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minItems: 2
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maxItems: 8
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items:
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- description: region used for dynamic DMA allocations like vrings and
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vring buffers
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- description: region reserved for firmware image sections
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additionalItems: true
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# Optional properties:
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# --------------------
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# The following properties are optional properties for each of the R5F cores:
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ti,atcm-enable:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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description: |
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R5F core configuration mode dictating if ATCM should be enabled. The
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R5F address of ATCM is dictated by ti,loczrama property. Should be
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either a value of 1 (enabled) or 0 (disabled), default is disabled
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if omitted. Recommended to enable it for maximizing TCMs.
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ti,btcm-enable:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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description: |
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R5F core configuration mode dictating if BTCM should be enabled. The
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R5F address of BTCM is dictated by ti,loczrama property. Should be
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either a value of 1 (enabled) or 0 (disabled), default is enabled if
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omitted.
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ti,loczrama:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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description: |
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R5F core configuration mode dictating which TCM should appear at
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address 0 (from core's view). Should be either a value of 1 (ATCM
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at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
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sram:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 4
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items:
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maxItems: 1
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description: |
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phandles to one or more reserved on-chip SRAM regions. The regions
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should be defined as child nodes of the respective SRAM node, and
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should be defined as per the generic bindings in,
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Documentation/devicetree/bindings/sram/sram.yaml
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required:
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- compatible
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- reg
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- reg-names
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- ti,sci
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- ti,sci-dev-id
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- ti,sci-proc-ids
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- resets
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- firmware-name
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unevaluatedProperties: false
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if:
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properties:
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compatible:
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enum:
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- ti,am64-r5fss
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then:
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properties:
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ti,cluster-mode:
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enum: [0, 2]
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else:
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properties:
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ti,cluster-mode:
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enum: [0, 1]
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required:
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- compatible
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- power-domains
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- "#address-cells"
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- "#size-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mailbox0: mailbox-0 {
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#mbox-cells = <1>;
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};
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mailbox1: mailbox-1 {
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#mbox-cells = <1>;
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};
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bus@100000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
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bus@28380000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
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/* AM65x MCU R5FSS node */
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mcu_r5fss0: r5fss@41000000 {
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compatible = "ti,am654-r5fss";
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power-domains = <&k3_pds 129>;
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ti,cluster-mode = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x41000000 0x00 0x41000000 0x20000>,
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<0x41400000 0x00 0x41400000 0x20000>;
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mcu_r5f0: r5f@41000000 {
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compatible = "ti,am654-r5f";
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reg = <0x41000000 0x00008000>,
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<0x41010000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <159>;
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ti,sci-proc-ids = <0x01 0xFF>;
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resets = <&k3_reset 159 1>;
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firmware-name = "am65x-mcu-r5f0_0-fw";
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ti,atcm-enable = <1>;
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ti,btcm-enable = <1>;
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ti,loczrama = <1>;
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mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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sram = <&mcu_r5fss0_core0_sram>;
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};
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mcu_r5f1: r5f@41400000 {
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compatible = "ti,am654-r5f";
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reg = <0x41400000 0x00008000>,
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<0x41410000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <245>;
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ti,sci-proc-ids = <0x02 0xFF>;
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resets = <&k3_reset 245 1>;
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firmware-name = "am65x-mcu-r5f0_1-fw";
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ti,atcm-enable = <1>;
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ti,btcm-enable = <1>;
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ti,loczrama = <1>;
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mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
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};
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};
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};
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};
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};
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