85 lines
2.4 KiB
YAML
85 lines
2.4 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX8MQ IOMUX Controller
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maintainers:
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- Anson Huang <Anson.Huang@nxp.com>
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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properties:
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compatible:
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const: fsl,imx8mq-iomuxc
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last
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integer CONFIG is the pad setting value like pull-up on this pin. Please
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refer to i.MX8M Quad Reference Manual for detailed CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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"mux_reg" indicates the offset of mux register.
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- description: |
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"conf_reg" indicates the offset of pad configuration register.
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- description: |
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_val" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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"pad_setting" indicates the pad configuration value to be applied.
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required:
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- fsl,pins
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additionalProperties: false
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allOf:
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- $ref: "pinctrl.yaml#"
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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# Pinmux controller node
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- |
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mq-iomuxc";
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reg = <0x30330000 0x10000>;
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pinctrl_uart1: uart1grp {
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fsl,pins =
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<0x234 0x49C 0x4F4 0x0 0x0 0x49>,
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<0x238 0x4A0 0x4F4 0x0 0x0 0x49>;
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};
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};
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...
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