280 lines
7.6 KiB
YAML
280 lines
7.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
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maintainers:
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- Grygorii Strashko <grygorii.strashko@ti.com>
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- Sekhar Nori <nsekhar@ti.com>
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description:
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The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
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(one external) and provides Ethernet packet communication for the device.
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The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
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(two external) and provides Ethernet packet communication and switching.
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The internal Communications Port Programming Interface (CPPI5) (Host port 0).
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Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
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and one RX channels and operating by NAVSS Unified DMA Peripheral Root
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Complex (UDMA-P) controller.
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CPSWxG features
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updated Address Lookup Engine (ALE).
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priority level Quality Of Service (QOS) support (802.1p)
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Support for Audio/Video Bridging (P802.1Qav/D6.0)
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Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
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Flow Control (802.3x) Support
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Time Sensitive Network Support
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IEEE P902.3br/D2.0 Interspersing Express Traffic
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IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
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Configurable number of addresses plus VLANs
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Configurable number of classifier/policers
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VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
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ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
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RX/TX csum offload
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Management Data Input/Output (MDIO) interface for PHYs management
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RMII/RGMII Interfaces support
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new version of Common Platform Time Sync (CPTS)
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The CPSWxG NUSS is integrated into
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device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
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device MAIN domain named CPSW0 on AM642x SoC.
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Specifications can be found at
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https://www.ti.com/lit/pdf/spruid7
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https://www.ti.com/lit/zip/spruil1
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https://www.ti.com/lit/pdf/spruim2
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properties:
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"#address-cells": true
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"#size-cells": true
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compatible:
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enum:
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- ti,am654-cpsw-nuss
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- ti,j7200-cpswxg-nuss
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- ti,j721e-cpsw-nuss
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- ti,am642-cpsw-nuss
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reg:
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maxItems: 1
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description:
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The physical base address and size of full the CPSWxG NUSS IO range
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reg-names:
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items:
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- const: cpsw_nuss
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ranges: true
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dma-coherent: true
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clocks:
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maxItems: 1
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description: CPSWxG NUSS functional clock
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clock-names:
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items:
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- const: fck
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assigned-clock-parents: true
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assigned-clocks: true
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power-domains:
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maxItems: 1
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dmas:
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maxItems: 9
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dma-names:
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items:
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- const: tx0
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- const: tx1
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- const: tx2
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- const: tx3
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- const: tx4
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- const: tx5
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- const: tx6
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- const: tx7
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- const: rx
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ethernet-ports:
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^port@[1-4]$":
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type: object
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description: CPSWxG NUSS external ports
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$ref: ethernet-controller.yaml#
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unevaluatedProperties: false
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properties:
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reg:
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minimum: 1
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maximum: 4
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description: CPSW port number
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phys:
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maxItems: 1
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description: phandle on phy-gmii-sel PHY
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label:
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description: label associated with this port
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ti,mac-only:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Specifies the port works in mac-only mode.
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ti,syscon-efuse:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: Phandle to the system control device node which
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provides access to efuse
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- description: offset to efuse registers???
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description:
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Phandle to the system control device node which provides access
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to efuse IO range with MAC addresses
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required:
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- reg
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- phys
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additionalProperties: false
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patternProperties:
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"^mdio@[0-9a-f]+$":
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type: object
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$ref: "ti,davinci-mdio.yaml#"
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description:
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CPSW MDIO bus.
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"^cpts@[0-9a-f]+":
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type: object
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$ref: "ti,k3-am654-cpts.yaml#"
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description:
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CPSW Common Platform Time Sync (CPTS) module.
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required:
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- compatible
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- reg
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- reg-names
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- ranges
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- clocks
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- clock-names
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- power-domains
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- dmas
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- dma-names
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- '#address-cells'
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- '#size-cells'
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allOf:
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- if:
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not:
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properties:
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compatible:
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contains:
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const: ti,j7200-cpswxg-nuss
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then:
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properties:
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ethernet-ports:
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patternProperties:
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"^port@[3-4]$": false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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mcu_cpsw: ethernet@46000000 {
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compatible = "ti,am654-cpsw-nuss";
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0x46000000 0x0 0x200000>;
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reg-names = "cpsw_nuss";
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ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
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dma-coherent;
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clocks = <&k3_clks 5 10>;
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clock-names = "fck";
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power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
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dmas = <&mcu_udmap 0xf000>,
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<&mcu_udmap 0xf001>,
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<&mcu_udmap 0xf002>,
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<&mcu_udmap 0xf003>,
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<&mcu_udmap 0xf004>,
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<&mcu_udmap 0xf005>,
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<&mcu_udmap 0xf006>,
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<&mcu_udmap 0xf007>,
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<&mcu_udmap 0x7000>;
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dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
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"rx";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw_port1: port@1 {
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reg = <1>;
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ti,mac-only;
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label = "port1";
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ti,syscon-efuse = <&mcu_conf 0x200>;
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phys = <&phy_gmii_sel 1>;
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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};
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};
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davinci_mdio: mdio@f00 {
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
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reg = <0x0 0xf00 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 5 10>;
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clock-names = "fck";
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bus_freq = <1000000>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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};
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cpts@3d000 {
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compatible = "ti,am65-cpts";
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reg = <0x0 0x3d000 0x0 0x400>;
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clocks = <&k3_clks 18 2>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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};
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};
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