447 lines
11 KiB
YAML
447 lines
11 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Frame Engine Ethernet controller
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maintainers:
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- Lorenzo Bianconi <lorenzo@kernel.org>
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- Felix Fietkau <nbd@nbd.name>
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description:
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The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
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have dual GMAC ports.
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properties:
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compatible:
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enum:
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- mediatek,mt2701-eth
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- mediatek,mt7623-eth
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- mediatek,mt7622-eth
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- mediatek,mt7629-eth
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- mediatek,mt7986-eth
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- ralink,rt5350-eth
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reg:
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maxItems: 1
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clocks: true
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clock-names: true
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interrupts:
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minItems: 3
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maxItems: 4
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power-domains:
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maxItems: 1
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resets:
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maxItems: 3
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reset-names:
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items:
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- const: fe
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- const: gmac
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- const: ppe
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mediatek,ethsys:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon node that handles the port setup.
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cci-control-port: true
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mediatek,hifsys:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the mediatek hifsys controller used to provide various clocks
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and reset to the system.
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mediatek,sgmiisys:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 2
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items:
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maxItems: 1
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description:
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A list of phandle to the syscon node that handles the SGMII setup which is required for
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those SoCs equipped with SGMII.
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mediatek,wed:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 2
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maxItems: 2
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items:
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maxItems: 1
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description:
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List of phandles to wireless ethernet dispatch nodes.
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dma-coherent: true
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mdio-bus:
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$ref: mdio.yaml#
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unevaluatedProperties: false
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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allOf:
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- $ref: "ethernet-controller.yaml#"
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt2701-eth
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- mediatek,mt7623-eth
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then:
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properties:
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interrupts:
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maxItems: 3
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: ethif
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- const: esw
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- const: gp1
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- const: gp2
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mediatek,pctl:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon node that handles the ports slew rate and
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driver current.
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mediatek,wed: false
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt7622-eth
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then:
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properties:
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interrupts:
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maxItems: 3
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clocks:
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minItems: 11
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maxItems: 11
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clock-names:
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items:
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- const: ethif
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- const: esw
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- const: gp0
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- const: gp1
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- const: gp2
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- const: sgmii_tx250m
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- const: sgmii_rx250m
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- const: sgmii_cdr_ref
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- const: sgmii_cdr_fb
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- const: sgmii_ck
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- const: eth2pll
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mediatek,sgmiisys:
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minItems: 1
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maxItems: 1
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mediatek,pcie-mirror:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the mediatek pcie-mirror controller.
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt7629-eth
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then:
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properties:
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interrupts:
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maxItems: 3
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clocks:
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minItems: 17
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maxItems: 17
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clock-names:
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items:
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- const: ethif
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- const: sgmiitop
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- const: esw
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- const: gp0
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- const: gp1
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- const: gp2
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- const: fe
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- const: sgmii_tx250m
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- const: sgmii_rx250m
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- const: sgmii_cdr_ref
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- const: sgmii_cdr_fb
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- const: sgmii2_tx250m
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- const: sgmii2_rx250m
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- const: sgmii2_cdr_ref
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- const: sgmii2_cdr_fb
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- const: sgmii_ck
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- const: eth2pll
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mediatek,infracfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon node that handles the path from GMAC to
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PHY variants.
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mediatek,sgmiisys:
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minItems: 2
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maxItems: 2
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mediatek,wed: false
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt7986-eth
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then:
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properties:
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interrupts:
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minItems: 4
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clocks:
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minItems: 15
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maxItems: 15
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clock-names:
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items:
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- const: fe
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- const: gp2
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- const: gp1
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- const: wocpu1
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- const: wocpu0
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- const: sgmii_tx250m
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- const: sgmii_rx250m
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- const: sgmii_cdr_ref
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- const: sgmii_cdr_fb
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- const: sgmii2_tx250m
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- const: sgmii2_rx250m
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- const: sgmii2_cdr_ref
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- const: sgmii2_cdr_fb
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- const: netsys0
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- const: netsys1
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mediatek,sgmiisys:
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minItems: 2
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maxItems: 2
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mediatek,wed-pcie:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the mediatek wed-pcie controller.
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patternProperties:
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"^mac@[0-1]$":
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type: object
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additionalProperties: false
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allOf:
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- $ref: ethernet-controller.yaml#
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description:
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Ethernet MAC node
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properties:
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compatible:
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const: mediatek,eth-mac
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reg:
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maxItems: 1
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phy-handle: true
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phy-mode: true
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required:
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- reg
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- compatible
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- phy-handle
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- mediatek,ethsys
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/mt7622-clk.h>
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#include <dt-bindings/power/mt7622-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ethernet: ethernet@1b100000 {
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compatible = "mediatek,mt7622-eth";
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reg = <0 0x1b100000 0 0x20000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_ETH_SEL>,
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<ðsys CLK_ETH_ESW_EN>,
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<ðsys CLK_ETH_GP0_EN>,
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<ðsys CLK_ETH_GP1_EN>,
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<ðsys CLK_ETH_GP2_EN>,
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<&sgmiisys CLK_SGMII_TX250M_EN>,
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<&sgmiisys CLK_SGMII_RX250M_EN>,
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<&sgmiisys CLK_SGMII_CDR_REF>,
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<&sgmiisys CLK_SGMII_CDR_FB>,
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<&topckgen CLK_TOP_SGMIIPLL>,
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<&apmixedsys CLK_APMIXED_ETH2PLL>;
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clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
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"sgmii_tx250m", "sgmii_rx250m",
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"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
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"eth2pll";
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power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys>;
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cci-control-port = <&cci_control2>;
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mediatek,pcie-mirror = <&pcie_mirror>;
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mediatek,hifsys = <&hifsys>;
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dma-coherent;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio0: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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reg = <0>;
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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reg = <1>;
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};
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};
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/mt7622-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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eth: ethernet@15100000 {
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#define CLK_ETH_FE_EN 0
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#define CLK_ETH_WOCPU1_EN 3
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#define CLK_ETH_WOCPU0_EN 4
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#define CLK_TOP_NETSYS_SEL 43
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#define CLK_TOP_NETSYS_500M_SEL 44
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#define CLK_TOP_NETSYS_2X_SEL 46
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#define CLK_TOP_SGM_325M_SEL 47
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#define CLK_APMIXED_NET2PLL 1
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#define CLK_APMIXED_SGMPLL 3
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compatible = "mediatek,mt7986-eth";
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reg = <0 0x15100000 0 0x80000>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <ðsys CLK_ETH_FE_EN>,
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<ðsys CLK_ETH_GP2_EN>,
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<ðsys CLK_ETH_GP1_EN>,
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<ðsys CLK_ETH_WOCPU1_EN>,
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<ðsys CLK_ETH_WOCPU0_EN>,
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<&sgmiisys0 CLK_SGMII_TX250M_EN>,
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<&sgmiisys0 CLK_SGMII_RX250M_EN>,
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<&sgmiisys0 CLK_SGMII_CDR_REF>,
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<&sgmiisys0 CLK_SGMII_CDR_FB>,
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<&sgmiisys1 CLK_SGMII_TX250M_EN>,
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<&sgmiisys1 CLK_SGMII_RX250M_EN>,
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<&sgmiisys1 CLK_SGMII_CDR_REF>,
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<&sgmiisys1 CLK_SGMII_CDR_FB>,
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<&topckgen CLK_TOP_NETSYS_SEL>,
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<&topckgen CLK_TOP_NETSYS_SEL>;
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clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
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"sgmii_tx250m", "sgmii_rx250m",
|
||
|
|
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
||
|
|
"sgmii2_tx250m", "sgmii2_rx250m",
|
||
|
|
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
||
|
|
"netsys0", "netsys1";
|
||
|
|
mediatek,ethsys = <ðsys>;
|
||
|
|
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||
|
|
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
||
|
|
<&topckgen CLK_TOP_SGM_325M_SEL>;
|
||
|
|
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
|
||
|
|
<&apmixedsys CLK_APMIXED_SGMPLL>;
|
||
|
|
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
mdio: mdio-bus {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
phy5: ethernet-phy@0 {
|
||
|
|
compatible = "ethernet-phy-id67c9.de0a";
|
||
|
|
phy-mode = "2500base-x";
|
||
|
|
reset-gpios = <&pio 6 1>;
|
||
|
|
reset-deassert-us = <20000>;
|
||
|
|
reg = <5>;
|
||
|
|
};
|
||
|
|
|
||
|
|
phy6: ethernet-phy@1 {
|
||
|
|
compatible = "ethernet-phy-id67c9.de0a";
|
||
|
|
phy-mode = "2500base-x";
|
||
|
|
reg = <6>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mac0: mac@0 {
|
||
|
|
compatible = "mediatek,eth-mac";
|
||
|
|
phy-mode = "2500base-x";
|
||
|
|
phy-handle = <&phy5>;
|
||
|
|
reg = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mac1: mac@1 {
|
||
|
|
compatible = "mediatek,eth-mac";
|
||
|
|
phy-mode = "2500base-x";
|
||
|
|
phy-handle = <&phy6>;
|
||
|
|
reg = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|