147 lines
3.3 KiB
YAML
147 lines
3.3 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mux/reg-mux.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic register bitfield-based multiplexer controller bindings
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maintainers:
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- Peter Rosin <peda@axentia.se>
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description: |+
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Define register bitfields to be used to control multiplexers. The parent
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device tree node must be a device node to provide register r/w access.
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properties:
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compatible:
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enum:
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- reg-mux # parent device of mux controller is not syscon device
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- mmio-mux # parent device of mux controller is syscon device
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reg: true
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'#mux-control-cells':
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const: 1
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mux-reg-masks:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: register offset
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- description: pre-shifted bitfield mask
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description: Each entry pair describes a single mux control.
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idle-states: true
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required:
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- compatible
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- mux-reg-masks
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- '#mux-control-cells'
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additionalProperties: false
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examples:
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- |
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/* The parent device of mux controller is not a syscon device. */
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#include <dt-bindings/mux/mux.h>
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mux-controller {
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compatible = "reg-mux";
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#mux-control-cells = <1>;
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mux-reg-masks =
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<0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
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<0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
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};
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mdio-mux-1 {
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compatible = "mdio-mux-multiplexer";
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mux-controls = <&mux1 0>;
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mdio-parent-bus = <&emdio1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio@8 {
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reg = <0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mdio-mux-2 {
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compatible = "mdio-mux-multiplexer";
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mux-controls = <&mux1 1>;
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mdio-parent-bus = <&emdio2>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio@1 {
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reg = <0x1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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- |
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/* The parent device of mux controller is syscon device. */
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#include <dt-bindings/mux/mux.h>
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syscon@1000 {
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reg = <0x1000 0x100>;
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mux2: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks =
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<0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
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<0x3 0x40>; /* 1: reg 0x3, bit 6 */
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idle-states = <MUX_IDLE_AS_IS>, <0>;
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};
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};
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video-mux {
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compatible = "video-mux";
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mux-controls = <&mux2 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* inputs 0..3 */
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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};
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port@2 {
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reg = <2>;
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};
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port@3 {
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reg = <3>;
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};
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/* output */
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port@4 {
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reg = <4>;
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};
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};
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};
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...
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