80 lines
1.8 KiB
YAML
80 lines
1.8 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra20 SoC Memory Controller
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maintainers:
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- Dmitry Osipenko <digetx@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |
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The Tegra20 Memory Controller merges request streams from various client
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interfaces into request stream(s) for the various memory target devices,
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and returns response data to the various clients. The Memory Controller
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has a configurable arbitration algorithm to allow the user to fine-tune
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performance among the various clients.
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Tegra20 Memory Controller includes the GART (Graphics Address Relocation
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Table) which allows Memory Controller to provide a linear view of a
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fragmented memory pages.
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properties:
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compatible:
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const: nvidia,tegra20-mc-gart
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reg:
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items:
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- description: controller registers
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- description: GART registers
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: mc
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interrupts:
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maxItems: 1
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"#reset-cells":
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const: 1
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"#iommu-cells":
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const: 0
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"#interconnect-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- "#reset-cells"
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- "#iommu-cells"
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- "#interconnect-cells"
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additionalProperties: false
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examples:
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- |
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memory-controller@7000f000 {
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compatible = "nvidia,tegra20-mc-gart";
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reg = <0x7000f000 0x400>, /* Controller registers */
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<0x58000000 0x02000000>; /* GART aperture */
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clocks = <&clock_controller 32>;
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clock-names = "mc";
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interrupts = <0 77 4>;
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#iommu-cells = <0>;
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#reset-cells = <1>;
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#interconnect-cells = <1>;
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};
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