81 lines
1.9 KiB
YAML
81 lines
1.9 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek JPEG Decoder
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maintainers:
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- Xia Jiang <xia.jiang@mediatek.com>
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description: |-
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Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt8173-jpgdec
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- mediatek,mt2701-jpgdec
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- items:
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- enum:
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- mediatek,mt7623-jpgdec
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- const: mediatek,mt2701-jpgdec
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 2
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minItems: 2
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clock-names:
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items:
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- const: jpgdec-smi
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- const: jpgdec
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power-domains:
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maxItems: 1
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iommus:
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maxItems: 2
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description: |
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Points to the respective IOMMU block with master port as argument, see
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Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
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Ports are according to the HW.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- iommus
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/power/mt2701-power.h>
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jpegdec: jpegdec@15004000 {
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compatible = "mediatek,mt2701-jpgdec";
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reg = <0x15004000 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
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<&imgsys CLK_IMG_JPGDEC>;
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clock-names = "jpgdec-smi",
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"jpgdec";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
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<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
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};
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