236 lines
5.7 KiB
Plaintext
236 lines
5.7 KiB
Plaintext
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MIPI DSI (Display Serial Interface) busses
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==========================================
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The MIPI Display Serial Interface specifies a serial bus and a protocol for
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communication between a host and up to four peripherals. This document will
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define the syntax used to represent a DSI bus in a device tree.
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This document describes DSI bus-specific properties only or defines existing
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standard properties in the context of the DSI bus.
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Each DSI host provides a DSI bus. The DSI host controller's node contains a
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set of properties that characterize the bus. Child nodes describe individual
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peripherals on that bus.
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The following assumes that only a single peripheral is connected to a DSI
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host. Experience shows that this is true for the large majority of setups.
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DSI host
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========
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In addition to the standard properties and those defined by the parent bus of
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a DSI host, the following properties apply to a node representing a DSI host.
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Required properties:
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- #address-cells: The number of cells required to represent an address on the
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bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
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a maximum of 4 devices can be addressed on a single bus. Hence the value of
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this property should be 1.
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- #size-cells: Should be 0. There are cases where it makes sense to use a
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different value here. See below.
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Optional properties:
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- clock-master: boolean. Should be enabled if the host is being used in
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conjunction with another DSI host to drive the same peripheral. Hardware
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supporting such a configuration generally requires the data on both the busses
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to be driven by the same clock. Only the DSI host instance controlling this
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clock should contain this property.
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DSI peripheral
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==============
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Peripherals with DSI as control bus, or no control bus
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------------------------------------------------------
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Peripherals with the DSI bus as the primary control bus, or peripherals with
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no control bus but use the DSI bus to transmit pixel data are represented
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as child nodes of the DSI host's node. Properties described here apply to all
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DSI peripherals, but individual bindings may want to define additional,
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device-specific properties.
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Required properties:
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- reg: The virtual channel number of a DSI peripheral. Must be in the range
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from 0 to 3.
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Some DSI peripherals respond to more than a single virtual channel. In that
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case two alternative representations can be chosen:
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- The reg property can take multiple entries, one for each virtual channel
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that the peripheral responds to.
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- If the virtual channels that a peripheral responds to are consecutive, the
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#size-cells can be set to 1. The first cell of each entry in the reg
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property is the number of the first virtual channel and the second cell is
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the number of consecutive virtual channels.
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Peripherals with a different control bus
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----------------------------------------
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There are peripherals that have I2C/SPI (or some other non-DSI bus) as the
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primary control bus, but are also connected to a DSI bus (mostly for the data
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path). Connections between such peripherals and a DSI host can be represented
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using the graph bindings [1], [2].
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Peripherals that support dual channel DSI
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-----------------------------------------
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Peripherals with higher bandwidth requirements can be connected to 2 DSI
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busses. Each DSI bus/channel drives some portion of the pixel data (generally
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left/right half of each line of the display, or even/odd lines of the display).
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The graph bindings should be used to represent the multiple DSI busses that are
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connected to this peripheral. Each DSI host's output endpoint can be linked to
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an input endpoint of the DSI peripheral.
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[1] Documentation/devicetree/bindings/graph.txt
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[2] Documentation/devicetree/bindings/media/video-interfaces.txt
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Examples
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========
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- (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
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with different virtual channel configurations.
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- (4) is an example of a peripheral on a I2C control bus connected to a
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DSI host using of-graph bindings.
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- (5) is an example of 2 DSI hosts driving a dual-channel DSI peripheral,
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which uses I2C as its primary control bus.
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1)
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dsi-host {
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...
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#address-cells = <1>;
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#size-cells = <0>;
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/* peripheral responds to virtual channel 0 */
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peripheral@0 {
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compatible = "...";
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reg = <0>;
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};
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...
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};
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2)
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dsi-host {
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...
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#address-cells = <1>;
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#size-cells = <0>;
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/* peripheral responds to virtual channels 0 and 2 */
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peripheral@0 {
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compatible = "...";
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reg = <0, 2>;
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};
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...
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};
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3)
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dsi-host {
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...
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#address-cells = <1>;
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#size-cells = <1>;
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/* peripheral responds to virtual channels 1, 2 and 3 */
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peripheral@1 {
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compatible = "...";
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reg = <1 3>;
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};
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...
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};
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4)
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i2c-host {
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...
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dsi-bridge@35 {
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compatible = "...";
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reg = <0x35>;
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ports {
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...
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port {
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bridge_mipi_in: endpoint {
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remote-endpoint = <&host_mipi_out>;
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};
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};
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};
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};
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};
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dsi-host {
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...
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ports {
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...
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port {
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host_mipi_out: endpoint {
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remote-endpoint = <&bridge_mipi_in>;
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};
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};
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};
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};
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5)
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i2c-host {
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dsi-bridge@35 {
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compatible = "...";
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reg = <0x35>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dsi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi1_in: endpoint {
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remote-endpoint = <&dsi1_out>;
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};
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};
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};
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};
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};
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dsi0-host {
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...
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/*
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* this DSI instance drives the clock for both the host
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* controllers
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*/
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clock-master;
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ports {
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...
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port {
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dsi0_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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dsi1-host {
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...
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ports {
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...
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port {
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dsi1_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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};
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