134 lines
5.3 KiB
Plaintext
134 lines
5.3 KiB
Plaintext
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Binding for a type of flexgen structure found on certain
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STMicroelectronics consumer electronics SoC devices
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This structure includes:
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- a clock cross bar (represented by a mux element)
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- a pre and final dividers (represented by a divider and gate elements)
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Flexgen structure is a part of Clockgen[1].
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Please find an example below:
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Clockgen block diagram
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-------------------------------------------------------------------
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| Flexgen structure |
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| --------------------------------------------- |
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| | ------- -------- -------- | |
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clk_sysin | | | | | | | | |
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---|-----------------|-->| | | | | | | |
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| | | | | | | | | | |
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| | ------- | | | |Pre | |Final | | |
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| | |PLL0 | | | | |Dividers| |Dividers| | |
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| |->| | | | | | x32 | | x32 | | |
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| | | odf_0|----|-->| | | | | | | |
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| | ------- | | | | | | | | |
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| | | | | | | | | | |
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| | ------- | | Clock | | | | | | |
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| | |PLL1 | | | | | | | | | |
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| |->| | | | Cross | | | | | | |
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| | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
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| | | | | | Bar |====>| |====>| |===|=========>
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| | ------- | | | | | | | | |
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| | ------- | | | | | | | | |
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| | |QUADFS | | | | | | | | | |
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| |->| ch0|----|-->| | | | | | | |
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| | ch1|----|-->| | | | | | | |
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| | | | | | | | | | | |
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| | ch2|----|-->| | | DIV | | DIV | | |
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| | | | | | | 1 to | | 1 to | | |
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| | ch3|----|-->| | | 1024 | | 64 | | |
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| ------- | | | | | | | | |
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| | ------- -------- -------- | |
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| -------------------------------------------- |
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-------------------------------------------------------------------
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This binding uses the common clock binding[2].
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[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be:
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"st,flexgen"
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"st,flexgen-audio", "st,flexgen" (enable clock propagation on parent for
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audio use case)
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"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
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and activate synchronous mode)
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"st,flexgen-stih407-a0"
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"st,flexgen-stih410-a0"
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"st,flexgen-stih407-c0"
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"st,flexgen-stih410-c0"
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"st,flexgen-stih418-c0"
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"st,flexgen-stih407-d0"
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"st,flexgen-stih410-d0"
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"st,flexgen-stih407-d2"
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"st,flexgen-stih418-d2"
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"st,flexgen-stih407-d3"
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- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
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outputs).
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- clocks : must be set to the parent's phandle. it could be output clocks of
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a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
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- clock-output-names : List of strings used to name the clock outputs.
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Example:
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_c0_pll0 0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_quadfs 0>,
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<&clk_s_c0_quadfs 1>,
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<&clk_s_c0_quadfs 2>,
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<&clk_s_c0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-icn-gpu",
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"clk-fdma",
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"clk-nand",
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"clk-hva",
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"clk-proc-stfe",
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"clk-proc-tp",
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"clk-rx-icn-dmu",
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"clk-rx-icn-hva",
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"clk-icn-cpu",
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"clk-tx-icn-dmu",
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"clk-mmc-0",
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"clk-mmc-1",
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"clk-jpegdec",
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"clk-ext2fa9",
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"clk-ic-bdisp-0",
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"clk-ic-bdisp-1",
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"clk-pp-dmu",
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"clk-vid-dmu",
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"clk-dss-lpc",
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"clk-st231-aud-0",
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"clk-st231-gp-1",
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"clk-st231-dmu",
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"clk-icn-lmi",
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"clk-tx-icn-disp-1",
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"clk-icn-sbc",
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"clk-stfe-frc2",
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"clk-eth-phy",
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"clk-eth-ref-phyclk",
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"clk-flash-promip",
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"clk-main-disp",
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"clk-aux-disp",
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"clk-compo-dvp";
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};
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