72 lines
1.5 KiB
YAML
72 lines
1.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2022 Unisoc Inc.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: UMS512 Soc clock controller
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maintainers:
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- Orson Zhai <orsonzhai@gmail.com>
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- Baolin Wang <baolin.wang7@gmail.com>
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- Chunyan Zhang <zhang.lyra@gmail.com>
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properties:
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compatible:
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enum:
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- sprd,ums512-apahb-gate
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- sprd,ums512-ap-clk
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- sprd,ums512-aonapb-clk
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- sprd,ums512-pmu-gate
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- sprd,ums512-g0-pll
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- sprd,ums512-g2-pll
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- sprd,ums512-g3-pll
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- sprd,ums512-gc-pll
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- sprd,ums512-aon-gate
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- sprd,ums512-audcpapb-gate
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- sprd,ums512-audcpahb-gate
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- sprd,ums512-gpu-clk
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- sprd,ums512-mm-clk
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- sprd,ums512-mm-gate-clk
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- sprd,ums512-apapb-gate
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"#clock-cells":
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const: 1
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clocks:
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minItems: 1
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maxItems: 4
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description: |
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The input parent clock(s) phandle for the clock, only list
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fixed clocks which are declared in devicetree.
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clock-names:
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minItems: 1
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items:
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- const: ext-26m
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- const: ext-32k
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- const: ext-4m
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- const: rco-100m
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reg:
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maxItems: 1
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required:
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- compatible
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- '#clock-cells'
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- reg
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additionalProperties: false
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examples:
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- |
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ap_clk: clock-controller@20200000 {
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compatible = "sprd,ums512-ap-clk";
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reg = <0x20200000 0x1000>;
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clocks = <&ext_26m>;
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clock-names = "ext-26m";
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#clock-cells = <1>;
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};
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...
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