81 lines
2.1 KiB
YAML
81 lines
2.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos SoC Audio SubSystem clock controller
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maintainers:
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Tomasz Figa <tomasz.figa@gmail.com>
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description: |
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All available clocks are defined as preprocessor macros in
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include/dt-bindings/clock/exynos-audss-clk.h header.
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properties:
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compatible:
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enum:
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- samsung,exynos4210-audss-clock
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- samsung,exynos5250-audss-clock
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- samsung,exynos5410-audss-clock
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- samsung,exynos5420-audss-clock
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clocks:
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minItems: 2
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items:
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- description:
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Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
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used if not specified.
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- description:
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Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
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used if not specified.
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- description:
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Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
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specified.
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- description:
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PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
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- description:
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External i2s clock, parent of mout_i2s. "cdclk0" is used if not
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specified.
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clock-names:
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minItems: 2
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items:
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- const: pll_ref
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- const: pll_in
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- const: sclk_audio
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- const: sclk_pcm_in
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- const: cdclk
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"#clock-cells":
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const: 1
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- "#clock-cells"
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- reg
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additionalProperties: false
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examples:
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- |
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clock-controller@3810000 {
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compatible = "samsung,exynos5250-audss-clock";
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reg = <0x03810000 0x0c>;
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#clock-cells = <1>;
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clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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};
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