65 lines
1.3 KiB
YAML
65 lines
1.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Versaclock7 Programmable Clock Device Tree Bindings
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maintainers:
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- Alex Helms <alexander.helms.jy@renesas.com>
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description: |
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Renesas Versaclock7 is a family of configurable clock generator and
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jitter attenuator ICs with fractional and integer dividers.
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properties:
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'#clock-cells':
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const: 1
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compatible:
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enum:
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- renesas,rc21008a
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reg:
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maxItems: 1
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clocks:
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items:
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- description: External crystal or oscillator
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clock-names:
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items:
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- const: xin
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required:
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- '#clock-cells'
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- compatible
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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vc7_xin: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <49152000>;
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};
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i2c@0 {
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reg = <0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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vc7: clock-controller@9 {
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compatible = "renesas,rc21008a";
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reg = <0x9>;
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#clock-cells = <1>;
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clocks = <&vc7_xin>;
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clock-names = "xin";
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};
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};
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