156 lines
6.2 KiB
Plaintext
156 lines
6.2 KiB
Plaintext
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NVIDIA Tegra124 DFLL FCPU clocksource
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The DFLL IP block on Tegra is a root clocksource designed for clocking
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the fast CPU cluster. It consists of a free-running voltage controlled
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oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
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control module that will automatically adjust the VDD_CPU voltage by
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communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
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Required properties:
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- compatible : should be one of:
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- "nvidia,tegra124-dfll": for Tegra124
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- "nvidia,tegra210-dfll": for Tegra210
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- reg : Defines the following set of registers, in the order listed:
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- registers for the DFLL control logic.
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- registers for the I2C output logic.
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- registers for the integrated I2C master controller.
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- look-up table RAM for voltage register values.
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- interrupts: Should contain the DFLL block interrupt.
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- clocks: Must contain an entry for each entry in clock-names.
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See clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- soc: Clock source for the DFLL control logic.
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- ref: The closed loop reference clock
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- i2c: Clock source for the integrated I2C master.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- dvco: Reset control for the DFLL DVCO.
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- #clock-cells: Must be 0.
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- clock-output-names: Name of the clock output.
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- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
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hardware will start controlling. The regulator will be queried for
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the I2C register, control values and supported voltages.
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Required properties for the control loop parameters:
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- nvidia,sample-rate: Sample rate of the DFLL control loop.
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- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
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- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
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- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
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- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
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- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
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Optional properties for the control loop parameters:
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- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
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Optional properties for mode selection:
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- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
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Required properties for I2C mode:
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- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
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Required properties for PWM mode:
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- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
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- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
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control is disabled and the PWM output is tristated. Note that this voltage is
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configured in hardware, typically via a resistor divider.
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- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
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is enabled and PWM output is low. Hence, this is the minimum output voltage
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that the regulator supports when PWM control is enabled.
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- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
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corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
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duty cycle would be: nvidia,pwm-min-microvolts +
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nvidia,pwm-voltage-step-microvolts * 2.
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- pinctrl-0: I/O pad configuration when PWM control is enabled.
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- pinctrl-1: I/O pad configuration when PWM control is disabled.
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- pinctrl-names: must include the following entries:
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- dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
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- dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
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Example for I2C:
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clock@70110000 {
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compatible = "nvidia,tegra124-dfll";
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reg = <0 0x70110000 0 0x100>, /* DFLL control */
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<0 0x70110000 0 0x100>, /* I2C output control */
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<0 0x70110100 0 0x100>, /* Integrated I2C controller */
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<0 0x70110200 0 0x100>; /* Look-up table RAM */
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
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<&tegra_car TEGRA124_CLK_DFLL_REF>,
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<&tegra_car TEGRA124_CLK_I2C5>;
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clock-names = "soc", "ref", "i2c";
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resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
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reset-names = "dvco";
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#clock-cells = <0>;
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clock-output-names = "dfllCPU_out";
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vdd-cpu-supply = <&vdd_cpu>;
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nvidia,sample-rate = <12500>;
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nvidia,droop-ctrl = <0x00000f00>;
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nvidia,force-mode = <1>;
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nvidia,cf = <10>;
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nvidia,ci = <0>;
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nvidia,cg = <2>;
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nvidia,i2c-fs-rate = <400000>;
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};
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Example for PWM:
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clock@70110000 {
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compatible = "nvidia,tegra124-dfll";
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reg = <0 0x70110000 0 0x100>, /* DFLL control */
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<0 0x70110000 0 0x100>, /* I2C output control */
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<0 0x70110100 0 0x100>, /* Integrated I2C controller */
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<0 0x70110200 0 0x100>; /* Look-up table RAM */
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
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<&tegra_car TEGRA210_CLK_DFLL_REF>,
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<&tegra_car TEGRA124_CLK_I2C5>;;
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clock-names = "soc", "ref", "i2c";
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resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
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reset-names = "dvco";
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#clock-cells = <0>;
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clock-output-names = "dfllCPU_out";
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nvidia,sample-rate = <25000>;
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nvidia,droop-ctrl = <0x00000f00>;
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nvidia,force-mode = <1>;
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nvidia,cf = <6>;
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nvidia,ci = <0>;
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nvidia,cg = <2>;
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nvidia,pwm-min-microvolts = <708000>; /* 708mV */
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nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
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nvidia,pwm-to-pmic;
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nvidia,pwm-tristate-microvolts = <1000000>;
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nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
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pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
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pinctrl-0 = <&dvfs_pwm_active_state>;
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pinctrl-1 = <&dvfs_pwm_inactive_state>;
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};
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/* pinmux nodes added for completeness. Binding doc can be found in:
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* Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
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*/
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pinmux: pinmux@700008d4 {
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dvfs_pwm_active_state: dvfs_pwm_active {
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dvfs_pwm_pbb1 {
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nvidia,pins = "dvfs_pwm_pbb1";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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};
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dvfs_pwm_inactive_state: dvfs_pwm_inactive {
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dvfs_pwm_pbb1 {
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nvidia,pins = "dvfs_pwm_pbb1";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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};
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};
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