61 lines
1.3 KiB
YAML
61 lines
1.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip LAN966X Generic Clock Controller
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maintainers:
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- Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
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description: |
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The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
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ddr_clk and sys_clk. This clock controller generates and supplies
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clock to various peripherals within the SoC.
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properties:
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compatible:
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const: microchip,lan966x-gck
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reg:
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minItems: 1
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items:
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- description: Generic clock registers
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- description: Optional gate clock registers
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clocks:
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items:
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- description: CPU clock source
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- description: DDR clock source
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- description: System clock source
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clock-names:
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items:
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- const: cpu
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- const: ddr
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- const: sys
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clks: clock-controller@e00c00a8 {
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compatible = "microchip,lan966x-gck";
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#clock-cells = <1>;
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clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
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clock-names = "cpu", "ddr", "sys";
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reg = <0xe00c00a8 0x38>;
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};
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...
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