51 lines
1.1 KiB
YAML
51 lines
1.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding
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maintainers:
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- Jacky Bai <ping.bai@nxp.com>
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description: |
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On i.MX8ULP, The clock sources generation, distribution and management is
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under the control of several CGCs & PCCs modules. The PCC modules control
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software reset, clock selection, optional division and clock gating mode
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for peripherals.
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properties:
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compatible:
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enum:
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- fsl,imx8ulp-pcc3
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- fsl,imx8ulp-pcc4
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- fsl,imx8ulp-pcc5
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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# Peripheral Clock Control Module node:
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- |
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clock-controller@292d0000 {
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compatible = "fsl,imx8ulp-pcc3";
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reg = <0x292d0000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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