68 lines
1.3 KiB
YAML
68 lines
1.3 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0+
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A80 Display Engine Clock Controller
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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compatible:
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const: allwinner,sun9i-a80-de-clks
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: RAM Bus Clock
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- description: Module Clock
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clock-names:
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items:
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- const: mod
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- const: dram
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- const: bus
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resets:
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maxItems: 1
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required:
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- "#clock-cells"
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- "#reset-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sun9i-a80-ccu.h>
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#include <dt-bindings/reset/sun9i-a80-ccu.h>
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de_clocks: clock@3000000 {
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compatible = "allwinner,sun9i-a80-de-clks";
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reg = <0x03000000 0x30>;
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clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
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clock-names = "mod", "dram", "bus";
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resets = <&ccu RST_BUS_DE>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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...
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