390 lines
14 KiB
YAML
390 lines
14 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra Power Management Controller (PMC)
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jonathan Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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enum:
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- nvidia,tegra20-pmc
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- nvidia,tegra30-pmc
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- nvidia,tegra114-pmc
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- nvidia,tegra124-pmc
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- nvidia,tegra210-pmc
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reg:
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maxItems: 1
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description:
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Offset and length of the register set for the device.
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clock-names:
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items:
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- const: pclk
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- const: clk32k_in
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description:
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Must includes entries pclk and clk32k_in.
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pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
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input to Tegra.
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clocks:
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maxItems: 2
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description:
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Must contain an entry for each entry in clock-names.
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See ../clocks/clocks-bindings.txt for details.
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'#clock-cells':
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const: 1
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description:
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Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
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PMC also has blink control which allows 32Khz clock output to
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Tegra blink pad.
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Consumer of PMC clock should specify the desired clock by having
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the clock ID in its "clocks" phandle cell with pmc clock provider.
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See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
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clock IDs.
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'#interrupt-cells':
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const: 2
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description:
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Specifies number of cells needed to encode an interrupt source.
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The value must be 2.
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interrupt-controller: true
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nvidia,invert-interrupt:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and
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then fed into the ARM GIC. The PMC is not involved in the detection
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or handling of this interrupt signal, merely its inversion.
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nvidia,core-power-req-active-high:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Core power request active-high.
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nvidia,sys-clock-req-active-high:
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$ref: /schemas/types.yaml#/definitions/flag
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description: System clock request active-high.
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nvidia,combined-power-req:
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$ref: /schemas/types.yaml#/definitions/flag
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description: combined power request for CPU and Core.
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nvidia,cpu-pwr-good-en:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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CPU power good signal from external PMIC to PMC is enabled.
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nvidia,suspend-mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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description:
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The suspend mode that the platform should use.
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Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
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Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
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Mode 2 is for LP2, CPU voltage off
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nvidia,cpu-pwr-good-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: CPU power good time in uSec.
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nvidia,cpu-pwr-off-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: CPU power off time in uSec.
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nvidia,core-pwr-good-time:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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<Oscillator-stable-time Power-stable-time>
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Core power good time in uSec.
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nvidia,core-pwr-off-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Core power off time in uSec.
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nvidia,lp0-vec:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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<start length> Starting address and length of LP0 vector.
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The LP0 vector contains the warm boot code that is executed
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by AVP when resuming from the LP0 state.
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The AVP (Audio-Video Processor) is an ARM7 processor and
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always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed
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from the deep sleep mode, the warm boot code will restore
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some PLLs, clocks and then brings up CPU0 for resuming the
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system.
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i2c-thermtrip:
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type: object
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description:
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On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
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hardware-triggered thermal reset will be enabled.
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properties:
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nvidia,i2c-controller-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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ID of I2C controller to send poweroff command to PMU.
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Valid values are described in section 9.2.148
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"APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
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Manual.
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nvidia,bus-addr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Bus address of the PMU on the I2C bus.
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nvidia,reg-addr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: PMU I2C register address to issue poweroff command.
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nvidia,reg-data:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Poweroff command to write to PMU.
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nvidia,pinmux-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Pinmux used by the hardware when issuing Poweroff command.
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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required:
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- nvidia,i2c-controller-id
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- nvidia,bus-addr
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- nvidia,reg-addr
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- nvidia,reg-data
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additionalProperties: false
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powergates:
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type: object
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description: |
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This node contains a hierarchy of power domain nodes, which should
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match the powergates on the Tegra SoC. Each powergate node
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represents a power-domain on the Tegra SoC that can be power-gated
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by the Tegra PMC.
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Hardware blocks belonging to a power domain should contain
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"power-domains" property that is a phandle pointing to corresponding
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powergate node.
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The name of the powergate node should be one of the below. Note that
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not every powergate is applicable to all Tegra devices and the following
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list shows which powergates are applicable to which devices.
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Please refer to Tegra TRM for mode details on the powergate nodes to
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use for each power-gate block inside Tegra.
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Name Description Devices Applicable
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3d 3D Graphics Tegra20/114/124/210
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3d0 3D Graphics 0 Tegra30
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3d1 3D Graphics 1 Tegra30
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aud Audio Tegra210
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dfd Debug Tegra210
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dis Display A Tegra114/124/210
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disb Display B Tegra114/124/210
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heg 2D Graphics Tegra30/114/124/210
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iram Internal RAM Tegra124/210
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mpe MPEG Encode All
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nvdec NVIDIA Video Decode Engine Tegra210
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nvjpg NVIDIA JPEG Engine Tegra210
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pcie PCIE Tegra20/30/124/210
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sata SATA Tegra30/124/210
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sor Display interfaces Tegra124/210
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ve2 Video Encode Engine 2 Tegra210
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venc Video Encode Engine All
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vdec Video Decode Engine Tegra20/30/114/124
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vic Video Imaging Compositor Tegra124/210
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xusba USB Partition A Tegra114/124/210
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xusbb USB Partition B Tegra114/124/210
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xusbc USB Partition C Tegra114/124/210
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patternProperties:
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"^[a-z0-9]+$":
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type: object
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properties:
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clocks:
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minItems: 1
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maxItems: 8
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description:
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Must contain an entry for each clock required by the PMC
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for controlling a power-gate.
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See ../clocks/clock-bindings.txt document for more details.
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resets:
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minItems: 1
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maxItems: 8
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description:
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Must contain an entry for each reset required by the PMC
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for controlling a power-gate.
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See ../reset/reset.txt for more details.
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'#power-domain-cells':
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const: 0
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description: Must be 0.
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required:
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- clocks
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- resets
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- '#power-domain-cells'
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additionalProperties: false
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patternProperties:
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"^[a-f0-9]+-[a-f0-9]+$":
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type: object
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description:
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This is a Pad configuration node. On Tegra SOCs a pad is a set of
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pins which are configured as a group. The pin grouping is a fixed
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attribute of the hardware. The PMC can be used to set pad power state
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and signaling voltage. A pad can be either in active or power down mode.
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The support for power state and signaling voltage configuration varies
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depending on the pad in question. 3.3V and 1.8V signaling voltages
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are supported on pins where software controllable signaling voltage
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switching is available.
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The pad configuration state nodes are placed under the pmc node and they
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are referred to by the pinctrl client properties. For more information
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see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
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The pad name should be used as the value of the pins property in pin
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configuration nodes.
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The following pads are present on Tegra124 and Tegra132
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audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
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hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
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sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
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The following pads are present on Tegra210
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audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
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debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
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hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
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sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
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properties:
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pins:
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$ref: /schemas/types.yaml#/definitions/string
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description: Must contain name of the pad(s) to be configured.
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low-power-enable:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Configure the pad into power down mode.
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low-power-disable:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Configure the pad into active mode.
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power-source:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
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TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
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The values are defined in
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include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
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Power state can be configured on all Tegra124 and Tegra132
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pads. None of the Tegra124 or Tegra132 pads support signaling
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voltage switching.
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All of the listed Tegra210 pads except pex-cntrl support power
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state configuration. Signaling voltage switching is supported
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on below Tegra210 pads.
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audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
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sdmmc3, spi, spi-hv, and uart.
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required:
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- pins
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additionalProperties: false
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core-domain:
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type: object
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description: |
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The vast majority of hardware blocks of Tegra SoC belong to a
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Core power domain, which has a dedicated voltage rail that powers
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the blocks.
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properties:
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operating-points-v2:
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description:
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Should contain level, voltages and opp-supported-hw property.
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The supported-hw is a bitfield indicating SoC speedo or process
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ID mask.
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"#power-domain-cells":
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const: 0
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required:
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- operating-points-v2
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- "#power-domain-cells"
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additionalProperties: false
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core-supply:
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description:
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Phandle to voltage regulator connected to the SoC Core power rail.
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required:
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- compatible
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- reg
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- clock-names
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- clocks
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- '#clock-cells'
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additionalProperties: false
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dependencies:
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"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
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"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
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"nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
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examples:
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
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#include <dt-bindings/soc/tegra-pmc.h>
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tegra_pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x7000e400 0x400>;
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core-supply = <®ulator>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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#clock-cells = <1>;
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <0>;
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nvidia,cpu-pwr-good-time = <0>;
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nvidia,cpu-pwr-off-time = <0>;
|
||
|
|
nvidia,core-pwr-good-time = <4587 3876>;
|
||
|
|
nvidia,core-pwr-off-time = <39065>;
|
||
|
|
nvidia,core-power-req-active-high;
|
||
|
|
nvidia,sys-clock-req-active-high;
|
||
|
|
|
||
|
|
pd_core: core-domain {
|
||
|
|
operating-points-v2 = <&core_opp_table>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
powergates {
|
||
|
|
pd_audio: aud {
|
||
|
|
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||
|
|
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||
|
|
resets = <&tegra_car 198>;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pd_xusbss: xusba {
|
||
|
|
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||
|
|
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|