45 lines
1.0 KiB
YAML
45 lines
1.0 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2020 thingy.jp.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MStar/SigmaStar Armv7 SoC l3bridge
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maintainers:
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- Daniel Palmer <daniel@thingy.jp>
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description: |
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MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
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between the CPU and memory. This means that before DMA capable
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devices are allowed to run the pipeline must be flushed to ensure
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everything is in memory.
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The l3bridge region contains registers that allow such a flush
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to be triggered.
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This node is used by the platform code to find where the registers
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are and install a barrier that triggers the required pipeline flush.
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properties:
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compatible:
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items:
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- const: mstar,l3bridge
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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l3bridge: l3bridge@1f204400 {
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compatible = "mstar,l3bridge";
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reg = <0x1f204400 0x200>;
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};
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