58 lines
1.4 KiB
YAML
58 lines
1.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: MediaTek System Clock Controller for MT8186
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maintainers:
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description: |
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The clock architecture in MediaTek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The apmixedsys provides most of PLLs which generated from SoC 26m.
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The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
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The mcusys provides mux control to select the clock source in AP MCU.
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The device nodes also provide the system control capacity for configuration.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8186-mcusys
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- mediatek,mt8186-topckgen
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- mediatek,mt8186-infracfg_ao
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- mediatek,mt8186-apmixedsys
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8186-topckgen", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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