230 lines
9.0 KiB
YAML
230 lines
9.0 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Versatile Express and Juno Boards
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maintainers:
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- Sudeep Holla <sudeep.holla@arm.com>
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- Linus Walleij <linus.walleij@linaro.org>
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description: |+
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ARM's Versatile Express platform were built as reference designs for exploring
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multicore Cortex-A class systems. The Versatile Express family contains both
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32 bit (Aarch32) and 64 bit (Aarch64) systems.
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The board consist of a motherboard and one or more daughterboards (tiles). The
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motherboard provides a set of peripherals. Processor and RAM "live" on the
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tiles.
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The motherboard and each core tile should be described by a separate Device
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Tree source file, with the tile's description including the motherboard file
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using an include directive. As the motherboard can be initialized in one of
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two different configurations ("memory maps"), care must be taken to include
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the correct one.
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When a new generation of boards were introduced under the name "Juno", these
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shared to many common characteristics with the Versatile Express that the
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"arm,vexpress" compatible was retained in the root node, and these are
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included in this binding schema as well.
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The root node indicates the CPU SoC on the core tile, and this
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is a daughterboard to the main motherboard. The name used in the compatible
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string shall match the name given in the core tile's technical reference
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manual, followed by "arm,vexpress" as an additional compatible value. If
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further subvariants are released of the core tile, even more fine-granular
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compatible strings with up to three compatible strings are used.
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
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in MPCore configuration in a test chip on the core tile. See ARM
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DUI 0448I. This was the first Versatile Express platform.
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items:
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- const: arm,vexpress,v2p-ca9
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- const: arm,vexpress
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- description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
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in a test chip on the core tile. It is intended to evaluate NEON, FPU
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and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
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items:
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- const: arm,vexpress,v2p-ca5s
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- const: arm,vexpress
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- description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
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cores in a MPCore configuration in a test chip on the core tile. See
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ARM DUI 0604F.
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items:
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- const: arm,vexpress,v2p-ca15
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- const: arm,vexpress
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- description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
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A15 CPU cores in a test chip on the core tile. This is the first test
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chip called "TC1".
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items:
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- const: arm,vexpress,v2p-ca15,tc1
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- const: arm,vexpress,v2p-ca15
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- const: arm,vexpress
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- description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
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CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
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in a test chip on the core tile. See ARM DDI 0503I.
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items:
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- const: arm,vexpress,v2p-ca15_a7
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- const: arm,vexpress
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- description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
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cores in a test chip on the core tile. See ARM DDI 0498D.
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items:
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- const: arm,vexpress,v2f-1xv7,ca53x2
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- const: arm,vexpress,v2f-1xv7
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- const: arm,vexpress
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- description: Arm Versatile Express Juno "r0" (the first Juno board,
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V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
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AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
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cores in a big.LITTLE configuration. It also features the MALI T624
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GPU. See ARM document 100113_0000_07_en.
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items:
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- const: arm,juno
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- const: arm,vexpress
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- description: Arm Versatile Express Juno r1 Development Platform
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(V2M-Juno r1) was introduced mainly aimed at development of PCIe
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based systems. Juno r1 also has support for AXI masters placed on
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the TLX connectors to join the coherency domain. Otherwise it is the
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same configuration as Juno r0. See ARM document 100122_0100_06_en.
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items:
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- const: arm,juno-r1
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- const: arm,juno
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- const: arm,vexpress
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- description: Arm Versatile Express Juno r2 Development Platform
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(V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
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ARM document 100114_0200_04_en.
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items:
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- const: arm,juno-r2
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- const: arm,juno
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- const: arm,vexpress
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- description: Arm AEMv8a Versatile Express Real-Time System Model
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(VE RTSM) is a programmers view of the Versatile Express with Arm
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v8A hardware. See ARM DUI 0575D.
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items:
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- const: arm,rtsm_ve,aemv8a
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- const: arm,vexpress
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- description: Arm FVP (Fixed Virtual Platform) base model revision C
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See ARM Document 100964_1190_00_en.
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items:
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- const: arm,fvp-base-revc
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- const: arm,vexpress
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- description: Arm Foundation model for Aarch64
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items:
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- const: arm,foundation-aarch64
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- const: arm,vexpress
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arm,vexpress,position:
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description: When daughterboards are stacked on one site, their position
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in the stack be be described this attribute.
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$ref: '/schemas/types.yaml#/definitions/uint32'
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minimum: 0
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maximum: 3
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arm,vexpress,dcc:
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description: When describing tiles consisting of more than one DCC, its
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number can be specified with this attribute.
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$ref: '/schemas/types.yaml#/definitions/uint32'
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minimum: 0
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maximum: 3
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patternProperties:
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"^bus@[0-9a-f]+$":
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description: Static Memory Bus (SMB) node, if this exists it describes
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the connection between the motherboard and any tiles. Sometimes the
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compatible is placed directly under this node, sometimes it is placed
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in a subnode named "motherboard-bus". Sometimes the compatible includes
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"arm,vexpress,v2?-p1" sometimes (on software models) is is just
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"simple-bus". If the compatible is placed in the "motherboard-bus" node,
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it is stricter and always has two compatibles.
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type: object
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$ref: '/schemas/simple-bus.yaml'
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- arm,vexpress,v2m-p1
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- arm,vexpress,v2p-p1
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- const: simple-bus
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- const: simple-bus
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patternProperties:
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'^motherboard-bus@':
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type: object
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description: The motherboard description provides a single "motherboard"
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node using 2 address cells corresponding to the Static Memory Bus
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used between the motherboard and the tile. The first cell defines the
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Chip Select (CS) line number, the second cell address offset within
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the CS. All interrupt lines between the motherboard and the tile
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are active high and are described using single cell.
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properties:
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"#address-cells":
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const: 2
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"#size-cells":
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const: 1
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ranges: true
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compatible:
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items:
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- enum:
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- arm,vexpress,v2m-p1
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- arm,vexpress,v2p-p1
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- const: simple-bus
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arm,v2m-memory-map:
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description: This describes the memory map type.
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$ref: '/schemas/types.yaml#/definitions/string'
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enum:
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- rs1
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- rs2
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arm,hbi:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description: This indicates the ARM HBI (Hardware Board ID), this is
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ARM's unique board model ID, visible on the PCB's silkscreen.
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arm,vexpress,site:
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description: As Versatile Express can be configured in number of physically
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different setups, the device tree should describe platform topology.
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For this reason the root node and main motherboard node must define this
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property, describing the physical location of the children nodes.
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0 means motherboard site, while 1 and 2 are daughterboard sites, and
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0xf means "sisterboard" which is the site containing the main CPU tile.
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$ref: '/schemas/types.yaml#/definitions/uint32'
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minimum: 0
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maximum: 15
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required:
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- compatible
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additionalProperties:
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type: object
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required:
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- compatible
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- arm,vexpress,v2p-ca9
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- arm,vexpress,v2p-ca5s
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- arm,vexpress,v2p-ca15
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- arm,vexpress,v2p-ca15_a7
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- arm,vexpress,v2f-1xv7,ca53x2
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then:
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required:
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- arm,hbi
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additionalProperties: true
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...
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