205 lines
9.5 KiB
C
205 lines
9.5 KiB
C
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/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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/*
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* ARM specific definitions for NOLIBC
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* Copyright (C) 2017-2022 Willy Tarreau <w@1wt.eu>
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*/
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#ifndef _NOLIBC_ARCH_ARM_H
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#define _NOLIBC_ARCH_ARM_H
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/* O_* macros for fcntl/open are architecture-specific */
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#define O_RDONLY 0
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#define O_WRONLY 1
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#define O_RDWR 2
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#define O_CREAT 0x40
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#define O_EXCL 0x80
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#define O_NOCTTY 0x100
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#define O_TRUNC 0x200
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#define O_APPEND 0x400
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#define O_NONBLOCK 0x800
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#define O_DIRECTORY 0x4000
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/* The struct returned by the stat() syscall, 32-bit only, the syscall returns
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* exactly 56 bytes (stops before the unused array). In big endian, the format
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* differs as devices are returned as short only.
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*/
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struct sys_stat_struct {
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#if defined(__ARMEB__)
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unsigned short st_dev;
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unsigned short __pad1;
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#else
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unsigned long st_dev;
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#endif
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unsigned long st_ino;
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unsigned short st_mode;
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unsigned short st_nlink;
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unsigned short st_uid;
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unsigned short st_gid;
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#if defined(__ARMEB__)
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unsigned short st_rdev;
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unsigned short __pad2;
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#else
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unsigned long st_rdev;
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#endif
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unsigned long st_size;
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unsigned long st_blksize;
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unsigned long st_blocks;
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unsigned long st_atime;
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unsigned long st_atime_nsec;
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unsigned long st_mtime;
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unsigned long st_mtime_nsec;
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unsigned long st_ctime;
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unsigned long st_ctime_nsec;
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unsigned long __unused[2];
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};
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/* Syscalls for ARM in ARM or Thumb modes :
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* - registers are 32-bit
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* - stack is 8-byte aligned
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* ( http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4127.html)
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* - syscall number is passed in r7
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* - arguments are in r0, r1, r2, r3, r4, r5
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* - the system call is performed by calling svc #0
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* - syscall return comes in r0.
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* - only lr is clobbered.
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* - the arguments are cast to long and assigned into the target registers
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* which are then simply passed as registers to the asm code, so that we
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* don't have to experience issues with register constraints.
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* - the syscall number is always specified last in order to allow to force
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* some registers before (gcc refuses a %-register at the last position).
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*
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* Also, ARM supports the old_select syscall if newselect is not available
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*/
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#define __ARCH_WANT_SYS_OLD_SELECT
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#define my_syscall0(num) \
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({ \
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register long _num __asm__ ("r7") = (num); \
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register long _arg1 __asm__ ("r0"); \
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\
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__asm__ volatile ( \
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"svc #0\n" \
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: "=r"(_arg1) \
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: "r"(_num) \
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: "memory", "cc", "lr" \
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); \
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_arg1; \
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})
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#define my_syscall1(num, arg1) \
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({ \
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register long _num __asm__ ("r7") = (num); \
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register long _arg1 __asm__ ("r0") = (long)(arg1); \
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\
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__asm__ volatile ( \
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"svc #0\n" \
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: "=r"(_arg1) \
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: "r"(_arg1), \
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"r"(_num) \
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: "memory", "cc", "lr" \
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); \
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_arg1; \
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})
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#define my_syscall2(num, arg1, arg2) \
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({ \
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register long _num __asm__ ("r7") = (num); \
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register long _arg1 __asm__ ("r0") = (long)(arg1); \
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register long _arg2 __asm__ ("r1") = (long)(arg2); \
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\
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__asm__ volatile ( \
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"svc #0\n" \
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: "=r"(_arg1) \
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: "r"(_arg1), "r"(_arg2), \
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"r"(_num) \
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: "memory", "cc", "lr" \
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); \
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_arg1; \
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})
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#define my_syscall3(num, arg1, arg2, arg3) \
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({ \
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register long _num __asm__ ("r7") = (num); \
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register long _arg1 __asm__ ("r0") = (long)(arg1); \
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register long _arg2 __asm__ ("r1") = (long)(arg2); \
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register long _arg3 __asm__ ("r2") = (long)(arg3); \
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\
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__asm__ volatile ( \
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"svc #0\n" \
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: "=r"(_arg1) \
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: "r"(_arg1), "r"(_arg2), "r"(_arg3), \
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"r"(_num) \
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: "memory", "cc", "lr" \
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); \
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_arg1; \
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})
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#define my_syscall4(num, arg1, arg2, arg3, arg4) \
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({ \
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register long _num __asm__ ("r7") = (num); \
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register long _arg1 __asm__ ("r0") = (long)(arg1); \
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register long _arg2 __asm__ ("r1") = (long)(arg2); \
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register long _arg3 __asm__ ("r2") = (long)(arg3); \
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register long _arg4 __asm__ ("r3") = (long)(arg4); \
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\
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__asm__ volatile ( \
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"svc #0\n" \
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: "=r"(_arg1) \
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: "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), \
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"r"(_num) \
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: "memory", "cc", "lr" \
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); \
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_arg1; \
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})
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#define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) \
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({ \
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register long _num __asm__ ("r7") = (num); \
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register long _arg1 __asm__ ("r0") = (long)(arg1); \
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register long _arg2 __asm__ ("r1") = (long)(arg2); \
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register long _arg3 __asm__ ("r2") = (long)(arg3); \
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register long _arg4 __asm__ ("r3") = (long)(arg4); \
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register long _arg5 __asm__ ("r4") = (long)(arg5); \
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\
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__asm__ volatile ( \
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"svc #0\n" \
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: "=r" (_arg1) \
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: "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
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"r"(_num) \
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: "memory", "cc", "lr" \
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); \
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_arg1; \
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})
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/* startup code */
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__asm__ (".section .text\n"
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".weak _start\n"
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"_start:\n"
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#if defined(__THUMBEB__) || defined(__THUMBEL__)
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/* We enter here in 32-bit mode but if some previous functions were in
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* 16-bit mode, the assembler cannot know, so we need to tell it we're in
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* 32-bit now, then switch to 16-bit (is there a better way to do it than
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* adding 1 by hand ?) and tell the asm we're now in 16-bit mode so that
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* it generates correct instructions. Note that we do not support thumb1.
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*/
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".code 32\n"
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"add r0, pc, #1\n"
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"bx r0\n"
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".code 16\n"
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#endif
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"pop {%r0}\n" // argc was in the stack
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"mov %r1, %sp\n" // argv = sp
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"add %r2, %r1, %r0, lsl #2\n" // envp = argv + 4*argc ...
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"add %r2, %r2, $4\n" // ... + 4
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"and %r3, %r1, $-8\n" // AAPCS : sp must be 8-byte aligned in the
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"mov %sp, %r3\n" // callee, an bl doesn't push (lr=pc)
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"bl main\n" // main() returns the status code, we'll exit with it.
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"movs r7, $1\n" // NR_exit == 1
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"svc $0x00\n"
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"");
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#endif // _NOLIBC_ARCH_ARM_H
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