117 lines
3.2 KiB
C
117 lines
3.2 KiB
C
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on Apollolake and GeminiLake
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*/
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#include <sound/sof/ext_manifest4.h>
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#include "../ipc4-priv.h"
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#include "../sof-priv.h"
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#include "hda.h"
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#include "../sof-audio.h"
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static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = {
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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/* apollolake ops */
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struct snd_sof_dsp_ops sof_apl_ops;
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EXPORT_SYMBOL_NS(sof_apl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
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int sof_apl_ops_init(struct snd_sof_dev *sdev)
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{
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/* common defaults */
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memcpy(&sof_apl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
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/* probe/remove/shutdown */
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sof_apl_ops.shutdown = hda_dsp_shutdown;
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if (sdev->pdata->ipc_type == SOF_IPC) {
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/* doorbell */
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sof_apl_ops.irq_thread = hda_dsp_ipc_irq_thread;
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/* ipc */
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sof_apl_ops.send_msg = hda_dsp_ipc_send_msg;
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/* debug */
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sof_apl_ops.ipc_dump = hda_ipc_dump;
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}
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if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
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struct sof_ipc4_fw_data *ipc4_data;
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sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
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if (!sdev->private)
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return -ENOMEM;
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ipc4_data = sdev->private;
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ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
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ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_5;
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/* doorbell */
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sof_apl_ops.irq_thread = hda_dsp_ipc4_irq_thread;
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/* ipc */
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sof_apl_ops.send_msg = hda_dsp_ipc4_send_msg;
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/* debug */
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sof_apl_ops.ipc_dump = hda_ipc4_dump;
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}
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/* set DAI driver ops */
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hda_set_dai_drv_ops(sdev, &sof_apl_ops);
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/* debug */
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sof_apl_ops.debug_map = apl_dsp_debugfs;
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sof_apl_ops.debug_map_count = ARRAY_SIZE(apl_dsp_debugfs);
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/* firmware run */
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sof_apl_ops.run = hda_dsp_cl_boot_firmware;
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/* pre/post fw run */
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sof_apl_ops.post_fw_run = hda_dsp_post_fw_run;
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/* dsp core get/put */
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sof_apl_ops.core_get = hda_dsp_core_get;
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return 0;
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};
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EXPORT_SYMBOL_NS(sof_apl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
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const struct sof_intel_dsp_desc apl_chip_info = {
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/* Apollolake */
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.cores_num = 2,
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.init_core_mask = 1,
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.host_managed_cores_mask = GENMASK(1, 0),
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.ipc_req = HDA_DSP_REG_HIPCI,
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.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
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.ipc_ack = HDA_DSP_REG_HIPCIE,
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.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
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.ipc_ctl = HDA_DSP_REG_HIPCCTL,
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.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
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.rom_init_timeout = 150,
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.ssp_count = APL_SSP_COUNT,
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.ssp_base_offset = APL_SSP_BASE_OFFSET,
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.quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
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.check_ipc_irq = hda_dsp_check_ipc_irq,
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.cl_init = cl_dsp_init,
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.power_down_dsp = hda_power_down_dsp,
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.disable_interrupts = hda_dsp_disable_interrupts,
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.hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,
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};
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EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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