443 lines
14 KiB
C
443 lines
14 KiB
C
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/*
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* Copyright © 2014-2015 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef _UAPI_VC4_DRM_H_
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#define _UAPI_VC4_DRM_H_
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define DRM_VC4_SUBMIT_CL 0x00
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#define DRM_VC4_WAIT_SEQNO 0x01
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#define DRM_VC4_WAIT_BO 0x02
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#define DRM_VC4_CREATE_BO 0x03
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#define DRM_VC4_MMAP_BO 0x04
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#define DRM_VC4_CREATE_SHADER_BO 0x05
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#define DRM_VC4_GET_HANG_STATE 0x06
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#define DRM_VC4_GET_PARAM 0x07
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#define DRM_VC4_SET_TILING 0x08
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#define DRM_VC4_GET_TILING 0x09
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#define DRM_VC4_LABEL_BO 0x0a
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#define DRM_VC4_GEM_MADVISE 0x0b
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#define DRM_VC4_PERFMON_CREATE 0x0c
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#define DRM_VC4_PERFMON_DESTROY 0x0d
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#define DRM_VC4_PERFMON_GET_VALUES 0x0e
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#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
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#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
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#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
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#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
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#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
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#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
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#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
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#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
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#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
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#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
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#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
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#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
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#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)
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#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)
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#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)
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struct drm_vc4_submit_rcl_surface {
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__u32 hindex; /* Handle index, or ~0 if not present. */
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__u32 offset; /* Offset to start of buffer. */
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/*
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* Bits for either render config (color_write) or load/store packet.
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* Bits should all be 0 for MSAA load/stores.
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*/
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__u16 bits;
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#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
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__u16 flags;
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};
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/**
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* struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
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* engine.
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*
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* Drivers typically use GPU BOs to store batchbuffers / command lists and
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* their associated state. However, because the VC4 lacks an MMU, we have to
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* do validation of memory accesses by the GPU commands. If we were to store
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* our commands in BOs, we'd need to do uncached readback from them to do the
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* validation process, which is too expensive. Instead, userspace accumulates
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* commands and associated state in plain memory, then the kernel copies the
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* data to its own address space, and then validates and stores it in a GPU
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* BO.
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*/
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struct drm_vc4_submit_cl {
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/* Pointer to the binner command list.
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*
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* This is the first set of commands executed, which runs the
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* coordinate shader to determine where primitives land on the screen,
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* then writes out the state updates and draw calls necessary per tile
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* to the tile allocation BO.
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*/
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__u64 bin_cl;
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/* Pointer to the shader records.
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*
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* Shader records are the structures read by the hardware that contain
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* pointers to uniforms, shaders, and vertex attributes. The
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* reference to the shader record has enough information to determine
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* how many pointers are necessary (fixed number for shaders/uniforms,
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* and an attribute count), so those BO indices into bo_handles are
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* just stored as __u32s before each shader record passed in.
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*/
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__u64 shader_rec;
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/* Pointer to uniform data and texture handles for the textures
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* referenced by the shader.
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*
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* For each shader state record, there is a set of uniform data in the
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* order referenced by the record (FS, VS, then CS). Each set of
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* uniform data has a __u32 index into bo_handles per texture
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* sample operation, in the order the QPU_W_TMUn_S writes appear in
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* the program. Following the texture BO handle indices is the actual
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* uniform data.
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*
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* The individual uniform state blocks don't have sizes passed in,
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* because the kernel has to determine the sizes anyway during shader
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* code validation.
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*/
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__u64 uniforms;
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__u64 bo_handles;
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/* Size in bytes of the binner command list. */
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__u32 bin_cl_size;
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/* Size in bytes of the set of shader records. */
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__u32 shader_rec_size;
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/* Number of shader records.
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*
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* This could just be computed from the contents of shader_records and
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* the address bits of references to them from the bin CL, but it
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* keeps the kernel from having to resize some allocations it makes.
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*/
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__u32 shader_rec_count;
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/* Size in bytes of the uniform state. */
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__u32 uniforms_size;
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/* Number of BO handles passed in (size is that times 4). */
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__u32 bo_handle_count;
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/* RCL setup: */
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__u16 width;
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__u16 height;
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__u8 min_x_tile;
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__u8 min_y_tile;
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__u8 max_x_tile;
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__u8 max_y_tile;
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struct drm_vc4_submit_rcl_surface color_read;
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struct drm_vc4_submit_rcl_surface color_write;
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struct drm_vc4_submit_rcl_surface zs_read;
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struct drm_vc4_submit_rcl_surface zs_write;
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struct drm_vc4_submit_rcl_surface msaa_color_write;
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struct drm_vc4_submit_rcl_surface msaa_zs_write;
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__u32 clear_color[2];
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__u32 clear_z;
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__u8 clear_s;
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__u32 pad:24;
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#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
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/* By default, the kernel gets to choose the order that the tiles are
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* rendered in. If this is set, then the tiles will be rendered in a
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* raster order, with the right-to-left vs left-to-right and
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* top-to-bottom vs bottom-to-top dictated by
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* VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping
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* blits to be implemented using the 3D engine.
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*/
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#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
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#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
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#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
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__u32 flags;
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/* Returned value of the seqno of this render job (for the
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* wait ioctl).
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*/
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__u64 seqno;
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/* ID of the perfmon to attach to this job. 0 means no perfmon. */
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__u32 perfmonid;
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/* Syncobj handle to wait on. If set, processing of this render job
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* will not start until the syncobj is signaled. 0 means ignore.
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*/
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__u32 in_sync;
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/* Syncobj handle to export fence to. If set, the fence in the syncobj
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* will be replaced with a fence that signals upon completion of this
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* render job. 0 means ignore.
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*/
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__u32 out_sync;
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__u32 pad2;
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};
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/**
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* struct drm_vc4_wait_seqno - ioctl argument for waiting for
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* DRM_VC4_SUBMIT_CL completion using its returned seqno.
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*
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* timeout_ns is the timeout in nanoseconds, where "0" means "don't
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* block, just return the status."
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*/
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struct drm_vc4_wait_seqno {
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__u64 seqno;
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__u64 timeout_ns;
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};
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/**
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* struct drm_vc4_wait_bo - ioctl argument for waiting for
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* completion of the last DRM_VC4_SUBMIT_CL on a BO.
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*
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* This is useful for cases where multiple processes might be
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* rendering to a BO and you want to wait for all rendering to be
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* completed.
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*/
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struct drm_vc4_wait_bo {
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__u32 handle;
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__u32 pad;
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__u64 timeout_ns;
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};
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/**
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* struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
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*
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* There are currently no values for the flags argument, but it may be
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* used in a future extension.
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*/
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struct drm_vc4_create_bo {
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__u32 size;
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__u32 flags;
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/** Returned GEM handle for the BO. */
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__u32 handle;
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__u32 pad;
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};
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/**
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* struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
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*
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* This doesn't actually perform an mmap. Instead, it returns the
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* offset you need to use in an mmap on the DRM device node. This
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* means that tools like valgrind end up knowing about the mapped
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* memory.
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*
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* There are currently no values for the flags argument, but it may be
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* used in a future extension.
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*/
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struct drm_vc4_mmap_bo {
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/** Handle for the object being mapped. */
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__u32 handle;
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__u32 flags;
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/** offset into the drm node to use for subsequent mmap call. */
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__u64 offset;
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};
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/**
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* struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
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* shader BOs.
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*
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* Since allowing a shader to be overwritten while it's also being
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* executed from would allow privlege escalation, shaders must be
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* created using this ioctl, and they can't be mmapped later.
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*/
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struct drm_vc4_create_shader_bo {
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/* Size of the data argument. */
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__u32 size;
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/* Flags, currently must be 0. */
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__u32 flags;
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/* Pointer to the data. */
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__u64 data;
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/** Returned GEM handle for the BO. */
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__u32 handle;
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/* Pad, must be 0. */
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__u32 pad;
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};
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struct drm_vc4_get_hang_state_bo {
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__u32 handle;
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__u32 paddr;
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__u32 size;
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__u32 pad;
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};
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/**
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* struct drm_vc4_hang_state - ioctl argument for collecting state
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* from a GPU hang for analysis.
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*/
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struct drm_vc4_get_hang_state {
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/** Pointer to array of struct drm_vc4_get_hang_state_bo. */
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__u64 bo;
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/**
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* On input, the size of the bo array. Output is the number
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* of bos to be returned.
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*/
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__u32 bo_count;
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__u32 start_bin, start_render;
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__u32 ct0ca, ct0ea;
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__u32 ct1ca, ct1ea;
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__u32 ct0cs, ct1cs;
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__u32 ct0ra0, ct1ra0;
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__u32 bpca, bpcs;
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__u32 bpoa, bpos;
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__u32 vpmbase;
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__u32 dbge;
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__u32 fdbgo;
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__u32 fdbgb;
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__u32 fdbgr;
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__u32 fdbgs;
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__u32 errstat;
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/* Pad that we may save more registers into in the future. */
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__u32 pad[16];
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};
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#define DRM_VC4_PARAM_V3D_IDENT0 0
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#define DRM_VC4_PARAM_V3D_IDENT1 1
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#define DRM_VC4_PARAM_V3D_IDENT2 2
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#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
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#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
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#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
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#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
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#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7
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#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8
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struct drm_vc4_get_param {
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__u32 param;
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__u32 pad;
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__u64 value;
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};
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struct drm_vc4_get_tiling {
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__u32 handle;
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__u32 flags;
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__u64 modifier;
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};
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struct drm_vc4_set_tiling {
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__u32 handle;
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__u32 flags;
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__u64 modifier;
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};
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/**
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* struct drm_vc4_label_bo - Attach a name to a BO for debug purposes.
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*/
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struct drm_vc4_label_bo {
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__u32 handle;
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__u32 len;
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__u64 name;
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};
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/*
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* States prefixed with '__' are internal states and cannot be passed to the
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* DRM_IOCTL_VC4_GEM_MADVISE ioctl.
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*/
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#define VC4_MADV_WILLNEED 0
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#define VC4_MADV_DONTNEED 1
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#define __VC4_MADV_PURGED 2
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#define __VC4_MADV_NOTSUPP 3
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struct drm_vc4_gem_madvise {
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__u32 handle;
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__u32 madv;
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__u32 retained;
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__u32 pad;
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};
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enum {
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VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER,
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VC4_PERFCNT_FEP_VALID_PRIMS_RENDER,
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VC4_PERFCNT_FEP_CLIPPED_QUADS,
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VC4_PERFCNT_FEP_VALID_QUADS,
|
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VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL,
|
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VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL,
|
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VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL,
|
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VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE,
|
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VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE,
|
||
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VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF,
|
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VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT,
|
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VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING,
|
||
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VC4_PERFCNT_PSE_PRIMS_REVERSED,
|
||
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VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES,
|
||
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VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING,
|
||
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VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING,
|
||
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VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST,
|
||
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VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS,
|
||
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VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD,
|
||
|
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VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS,
|
||
|
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VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT,
|
||
|
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VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS,
|
||
|
|
VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT,
|
||
|
|
VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS,
|
||
|
|
VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED,
|
||
|
|
VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS,
|
||
|
|
VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED,
|
||
|
|
VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED,
|
||
|
|
VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT,
|
||
|
|
VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS,
|
||
|
|
VC4_PERFCNT_NUM_EVENTS,
|
||
|
|
};
|
||
|
|
|
||
|
|
#define DRM_VC4_MAX_PERF_COUNTERS 16
|
||
|
|
|
||
|
|
struct drm_vc4_perfmon_create {
|
||
|
|
__u32 id;
|
||
|
|
__u32 ncounters;
|
||
|
|
__u8 events[DRM_VC4_MAX_PERF_COUNTERS];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct drm_vc4_perfmon_destroy {
|
||
|
|
__u32 id;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Returns the values of the performance counters tracked by this
|
||
|
|
* perfmon (as an array of ncounters u64 values).
|
||
|
|
*
|
||
|
|
* No implicit synchronization is performed, so the user has to
|
||
|
|
* guarantee that any jobs using this perfmon have already been
|
||
|
|
* completed (probably by blocking on the seqno returned by the
|
||
|
|
* last exec that used the perfmon).
|
||
|
|
*/
|
||
|
|
struct drm_vc4_perfmon_get_values {
|
||
|
|
__u32 id;
|
||
|
|
__u64 values_ptr;
|
||
|
|
};
|
||
|
|
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _UAPI_VC4_DRM_H_ */
|