123 lines
4.2 KiB
C
123 lines
4.2 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H
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/* GCC clocks */
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#define GPLL0 0
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#define GPLL0_OUT_EVEN 1
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#define GCC_AHB_PCIE_LINK_CLK 2
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#define GCC_BLSP1_AHB_CLK 3
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 4
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 6
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 8
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 10
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 12
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 14
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 18
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19
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#define GCC_BLSP1_SLEEP_CLK 20
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#define GCC_BLSP1_UART1_APPS_CLK 21
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#define GCC_BLSP1_UART1_APPS_CLK_SRC 22
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#define GCC_BLSP1_UART2_APPS_CLK 23
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#define GCC_BLSP1_UART2_APPS_CLK_SRC 24
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#define GCC_BLSP1_UART3_APPS_CLK 25
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#define GCC_BLSP1_UART3_APPS_CLK_SRC 26
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#define GCC_BLSP1_UART4_APPS_CLK 27
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#define GCC_BLSP1_UART4_APPS_CLK_SRC 28
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#define GCC_BOOT_ROM_AHB_CLK 29
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#define GCC_CPUSS_AHB_CLK 30
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#define GCC_CPUSS_AHB_CLK_SRC 31
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32
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#define GCC_CPUSS_GNOC_CLK 33
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#define GCC_GP1_CLK 34
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#define GCC_GP1_CLK_SRC 35
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#define GCC_GP2_CLK 36
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#define GCC_GP2_CLK_SRC 37
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#define GCC_GP3_CLK 38
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#define GCC_GP3_CLK_SRC 39
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#define GCC_PCIE_0_CLKREF_EN 40
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#define GCC_PCIE_AUX_CLK 41
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#define GCC_PCIE_AUX_CLK_SRC 42
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#define GCC_PCIE_AUX_PHY_CLK_SRC 43
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#define GCC_PCIE_CFG_AHB_CLK 44
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#define GCC_PCIE_MSTR_AXI_CLK 45
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#define GCC_PCIE_PIPE_CLK 46
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#define GCC_PCIE_PIPE_CLK_SRC 47
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#define GCC_PCIE_RCHNG_PHY_CLK 48
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#define GCC_PCIE_RCHNG_PHY_CLK_SRC 49
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#define GCC_PCIE_SLEEP_CLK 50
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#define GCC_PCIE_SLV_AXI_CLK 51
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#define GCC_PCIE_SLV_Q2A_AXI_CLK 52
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#define GCC_PDM2_CLK 53
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#define GCC_PDM2_CLK_SRC 54
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#define GCC_PDM_AHB_CLK 55
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#define GCC_PDM_XO4_CLK 56
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#define GCC_RX1_USB2_CLKREF_EN 57
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#define GCC_SDCC1_AHB_CLK 58
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#define GCC_SDCC1_APPS_CLK 59
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#define GCC_SDCC1_APPS_CLK_SRC 60
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#define GCC_SPMI_FETCHER_AHB_CLK 61
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#define GCC_SPMI_FETCHER_CLK 62
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#define GCC_SPMI_FETCHER_CLK_SRC 63
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 64
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#define GCC_USB30_MASTER_CLK 65
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#define GCC_USB30_MASTER_CLK_SRC 66
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#define GCC_USB30_MOCK_UTMI_CLK 67
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#define GCC_USB30_MOCK_UTMI_CLK_SRC 68
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#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69
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#define GCC_USB30_MSTR_AXI_CLK 70
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#define GCC_USB30_SLEEP_CLK 71
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#define GCC_USB30_SLV_AHB_CLK 72
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#define GCC_USB3_PHY_AUX_CLK 73
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#define GCC_USB3_PHY_AUX_CLK_SRC 74
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#define GCC_USB3_PHY_PIPE_CLK 75
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#define GCC_USB3_PHY_PIPE_CLK_SRC 76
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#define GCC_USB3_PRIM_CLKREF_EN 77
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 78
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#define GCC_XO_DIV4_CLK 79
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#define GCC_XO_PCIE_LINK_CLK 80
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/* GCC resets */
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#define GCC_BLSP1_QUP1_BCR 0
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#define GCC_BLSP1_QUP2_BCR 1
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#define GCC_BLSP1_QUP3_BCR 2
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#define GCC_BLSP1_QUP4_BCR 3
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#define GCC_BLSP1_UART1_BCR 4
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#define GCC_BLSP1_UART2_BCR 5
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#define GCC_BLSP1_UART3_BCR 6
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#define GCC_BLSP1_UART4_BCR 7
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#define GCC_PCIE_BCR 8
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#define GCC_PCIE_LINK_DOWN_BCR 9
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#define GCC_PCIE_NOCSR_COM_PHY_BCR 10
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#define GCC_PCIE_PHY_BCR 11
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#define GCC_PCIE_PHY_CFG_AHB_BCR 12
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#define GCC_PCIE_PHY_COM_BCR 13
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#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14
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#define GCC_PDM_BCR 15
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#define GCC_QUSB2PHY_BCR 16
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#define GCC_SDCC1_BCR 17
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#define GCC_SPMI_FETCHER_BCR 18
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#define GCC_TCSR_PCIE_BCR 19
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#define GCC_USB30_BCR 20
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#define GCC_USB3_PHY_BCR 21
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#define GCC_USB3PHY_PHY_BCR 22
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
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/* GCC power domains */
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#define USB30_GDSC 0
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#define PCIE_GDSC 1
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#endif
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