117 lines
3.6 KiB
C
117 lines
3.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <haijun.liu@mediatek.com>
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* Eliot Lee <eliot.lee@intel.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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*
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* Contributors:
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* Amir Hanania <amir.hanania@intel.com>
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* Moises Veleta <moises.veleta@intel.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*/
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#ifndef __T7XX_HIF_DPMA_RX_H__
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#define __T7XX_HIF_DPMA_RX_H__
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#include <linux/bits.h>
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#include <linux/types.h>
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#include "t7xx_hif_dpmaif.h"
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#define NETIF_MASK GENMASK(4, 0)
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#define PKT_TYPE_IP4 0
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#define PKT_TYPE_IP6 1
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/* Structure of DL PIT */
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struct dpmaif_pit {
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__le32 header;
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union {
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struct {
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__le32 data_addr_l;
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__le32 data_addr_h;
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__le32 footer;
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} pd;
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struct {
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__le32 params_1;
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__le32 params_2;
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__le32 params_3;
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} msg;
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};
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};
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/* PIT header fields */
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#define PD_PIT_DATA_LEN GENMASK(31, 16)
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#define PD_PIT_BUFFER_ID GENMASK(15, 3)
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#define PD_PIT_BUFFER_TYPE BIT(2)
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#define PD_PIT_CONT BIT(1)
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#define PD_PIT_PACKET_TYPE BIT(0)
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/* PIT footer fields */
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#define PD_PIT_DLQ_DONE GENMASK(31, 30)
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#define PD_PIT_ULQ_DONE GENMASK(29, 24)
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#define PD_PIT_HEADER_OFFSET GENMASK(23, 19)
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#define PD_PIT_BI_F GENMASK(18, 17)
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#define PD_PIT_IG BIT(16)
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#define PD_PIT_RES GENMASK(15, 11)
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#define PD_PIT_H_BID GENMASK(10, 8)
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#define PD_PIT_PIT_SEQ GENMASK(7, 0)
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#define MSG_PIT_DP BIT(31)
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#define MSG_PIT_RES GENMASK(30, 27)
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#define MSG_PIT_NETWORK_TYPE GENMASK(26, 24)
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#define MSG_PIT_CHANNEL_ID GENMASK(23, 16)
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#define MSG_PIT_RES2 GENMASK(15, 12)
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#define MSG_PIT_HPC_IDX GENMASK(11, 8)
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#define MSG_PIT_SRC_QID GENMASK(7, 5)
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#define MSG_PIT_ERROR_BIT BIT(4)
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#define MSG_PIT_CHECKSUM GENMASK(3, 2)
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#define MSG_PIT_CONT BIT(1)
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#define MSG_PIT_PACKET_TYPE BIT(0)
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#define MSG_PIT_HP_IDX GENMASK(31, 27)
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#define MSG_PIT_CMD GENMASK(26, 24)
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#define MSG_PIT_RES3 GENMASK(23, 21)
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#define MSG_PIT_FLOW GENMASK(20, 16)
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#define MSG_PIT_COUNT GENMASK(15, 0)
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#define MSG_PIT_HASH GENMASK(31, 24)
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#define MSG_PIT_RES4 GENMASK(23, 18)
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#define MSG_PIT_PRO GENMASK(17, 16)
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#define MSG_PIT_VBID GENMASK(15, 3)
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#define MSG_PIT_RES5 GENMASK(2, 0)
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#define MSG_PIT_DLQ_DONE GENMASK(31, 30)
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#define MSG_PIT_ULQ_DONE GENMASK(29, 24)
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#define MSG_PIT_IP BIT(23)
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#define MSG_PIT_RES6 BIT(22)
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#define MSG_PIT_MR GENMASK(21, 20)
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#define MSG_PIT_RES7 GENMASK(19, 17)
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#define MSG_PIT_IG BIT(16)
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#define MSG_PIT_RES8 GENMASK(15, 11)
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#define MSG_PIT_H_BID GENMASK(10, 8)
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#define MSG_PIT_PIT_SEQ GENMASK(7, 0)
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int t7xx_dpmaif_rxq_init(struct dpmaif_rx_queue *queue);
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void t7xx_dpmaif_rx_clear(struct dpmaif_ctrl *dpmaif_ctrl);
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int t7xx_dpmaif_bat_rel_wq_alloc(struct dpmaif_ctrl *dpmaif_ctrl);
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int t7xx_dpmaif_rx_buf_alloc(struct dpmaif_ctrl *dpmaif_ctrl,
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const struct dpmaif_bat_request *bat_req,
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const unsigned int q_num, const unsigned int buf_cnt,
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const bool initial);
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int t7xx_dpmaif_rx_frag_alloc(struct dpmaif_ctrl *dpmaif_ctrl, struct dpmaif_bat_request *bat_req,
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const unsigned int buf_cnt, const bool first_time);
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void t7xx_dpmaif_rx_stop(struct dpmaif_ctrl *dpmaif_ctrl);
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void t7xx_dpmaif_irq_rx_done(struct dpmaif_ctrl *dpmaif_ctrl, const unsigned int que_mask);
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void t7xx_dpmaif_rxq_free(struct dpmaif_rx_queue *queue);
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void t7xx_dpmaif_bat_wq_rel(struct dpmaif_ctrl *dpmaif_ctrl);
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int t7xx_dpmaif_bat_alloc(const struct dpmaif_ctrl *dpmaif_ctrl, struct dpmaif_bat_request *bat_req,
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const enum bat_type buf_type);
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void t7xx_dpmaif_bat_free(const struct dpmaif_ctrl *dpmaif_ctrl,
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struct dpmaif_bat_request *bat_req);
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#endif /* __T7XX_HIF_DPMA_RX_H__ */
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