430 lines
11 KiB
C
430 lines
11 KiB
C
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/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include <linux/export.h>
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#define AR_BufLen 0x00000fff
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static void ar9002_hw_rx_enable(struct ath_hw *ah)
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{
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REG_WRITE(ah, AR_CR, AR_CR_RXE);
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}
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static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
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{
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((struct ath_desc*) ds)->ds_link = ds_link;
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}
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static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked,
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u32 *sync_cause_p)
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{
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u32 isr = 0;
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u32 mask2 = 0;
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struct ath9k_hw_capabilities *pCap = &ah->caps;
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u32 sync_cause = 0;
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bool fatal_int = false;
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struct ath_common *common = ath9k_hw_common(ah);
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if (!AR_SREV_9100(ah)) {
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if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
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if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
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== AR_RTC_STATUS_ON) {
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isr = REG_READ(ah, AR_ISR);
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}
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}
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sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
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AR_INTR_SYNC_DEFAULT;
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*masked = 0;
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if (!isr && !sync_cause)
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return false;
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} else {
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*masked = 0;
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isr = REG_READ(ah, AR_ISR);
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}
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if (isr) {
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if (isr & AR_ISR_BCNMISC) {
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u32 isr2;
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isr2 = REG_READ(ah, AR_ISR_S2);
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if (isr2 & AR_ISR_S2_TIM)
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mask2 |= ATH9K_INT_TIM;
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if (isr2 & AR_ISR_S2_DTIM)
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mask2 |= ATH9K_INT_DTIM;
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if (isr2 & AR_ISR_S2_DTIMSYNC)
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mask2 |= ATH9K_INT_DTIMSYNC;
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if (isr2 & (AR_ISR_S2_CABEND))
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mask2 |= ATH9K_INT_CABEND;
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if (isr2 & AR_ISR_S2_GTT)
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mask2 |= ATH9K_INT_GTT;
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if (isr2 & AR_ISR_S2_CST)
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mask2 |= ATH9K_INT_CST;
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if (isr2 & AR_ISR_S2_TSFOOR)
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mask2 |= ATH9K_INT_TSFOOR;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR_S2, isr2);
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isr &= ~AR_ISR_BCNMISC;
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}
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}
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if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
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isr = REG_READ(ah, AR_ISR_RAC);
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if (isr == 0xffffffff) {
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*masked = 0;
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return false;
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}
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*masked = isr & ATH9K_INT_COMMON;
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if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
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AR_ISR_RXOK | AR_ISR_RXERR))
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*masked |= ATH9K_INT_RX;
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if (isr &
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(AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
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AR_ISR_TXEOL)) {
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u32 s0_s, s1_s;
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*masked |= ATH9K_INT_TX;
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if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
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s0_s = REG_READ(ah, AR_ISR_S0_S);
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s1_s = REG_READ(ah, AR_ISR_S1_S);
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} else {
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s0_s = REG_READ(ah, AR_ISR_S0);
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REG_WRITE(ah, AR_ISR_S0, s0_s);
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s1_s = REG_READ(ah, AR_ISR_S1);
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REG_WRITE(ah, AR_ISR_S1, s1_s);
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isr &= ~(AR_ISR_TXOK |
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AR_ISR_TXDESC |
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AR_ISR_TXERR |
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AR_ISR_TXEOL);
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}
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ah->intr_txqs = MS(s0_s, AR_ISR_S0_QCU_TXOK);
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ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
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ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
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ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
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}
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if (isr & AR_ISR_RXORN) {
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ath_dbg(common, INTERRUPT,
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"receive FIFO overrun interrupt\n");
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}
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*masked |= mask2;
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}
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if (!AR_SREV_9100(ah) && (isr & AR_ISR_GENTMR)) {
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u32 s5_s;
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if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) {
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s5_s = REG_READ(ah, AR_ISR_S5_S);
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} else {
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s5_s = REG_READ(ah, AR_ISR_S5);
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}
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ah->intr_gen_timer_trigger =
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MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
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ah->intr_gen_timer_thresh =
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MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
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if (ah->intr_gen_timer_trigger)
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*masked |= ATH9K_INT_GENTIMER;
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if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
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!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
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*masked |= ATH9K_INT_TIM_TIMER;
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR_S5, s5_s);
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isr &= ~AR_ISR_GENTMR;
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}
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}
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
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REG_WRITE(ah, AR_ISR, isr);
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REG_READ(ah, AR_ISR);
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}
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if (AR_SREV_9100(ah))
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return true;
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if (sync_cause) {
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if (sync_cause_p)
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*sync_cause_p = sync_cause;
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fatal_int =
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(sync_cause &
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(AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
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? true : false;
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if (fatal_int) {
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if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
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ath_dbg(common, ANY,
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"received PCI FATAL interrupt\n");
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}
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if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
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ath_dbg(common, ANY,
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"received PCI PERR interrupt\n");
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}
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*masked |= ATH9K_INT_FATAL;
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}
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if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
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ath_dbg(common, INTERRUPT,
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"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
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REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
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REG_WRITE(ah, AR_RC, 0);
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*masked |= ATH9K_INT_FATAL;
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}
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if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
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ath_dbg(common, INTERRUPT,
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"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
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}
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REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
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(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
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}
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return true;
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}
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static void
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ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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u32 ctl1, ctl6;
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ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
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ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
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ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
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ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
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ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
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WRITE_ONCE(ads->ds_link, i->link);
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WRITE_ONCE(ads->ds_data, i->buf_addr[0]);
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ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore);
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ctl6 = SM(i->keytype, AR_EncrType);
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if (AR_SREV_9285(ah)) {
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ads->ds_ctl8 = 0;
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ads->ds_ctl9 = 0;
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ads->ds_ctl10 = 0;
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ads->ds_ctl11 = 0;
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}
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if ((i->is_first || i->is_last) &&
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i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
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WRITE_ONCE(ads->ds_ctl2, set11nTries(i->rates, 0)
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| set11nTries(i->rates, 1)
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| set11nTries(i->rates, 2)
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| set11nTries(i->rates, 3)
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| (i->dur_update ? AR_DurUpdateEna : 0)
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| SM(0, AR_BurstDur));
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WRITE_ONCE(ads->ds_ctl3, set11nRate(i->rates, 0)
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| set11nRate(i->rates, 1)
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| set11nRate(i->rates, 2)
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| set11nRate(i->rates, 3));
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} else {
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WRITE_ONCE(ads->ds_ctl2, 0);
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WRITE_ONCE(ads->ds_ctl3, 0);
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}
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if (!i->is_first) {
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WRITE_ONCE(ads->ds_ctl0, 0);
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WRITE_ONCE(ads->ds_ctl1, ctl1);
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WRITE_ONCE(ads->ds_ctl6, ctl6);
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return;
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}
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ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
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| SM(i->type, AR_FrameType)
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| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
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| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
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| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
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switch (i->aggr) {
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case AGGR_BUF_FIRST:
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ctl6 |= SM(i->aggr_len, AR_AggrLen);
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fallthrough;
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case AGGR_BUF_MIDDLE:
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ctl1 |= AR_IsAggr | AR_MoreAggr;
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ctl6 |= SM(i->ndelim, AR_PadDelim);
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break;
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case AGGR_BUF_LAST:
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ctl1 |= AR_IsAggr;
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break;
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case AGGR_BUF_NONE:
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break;
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}
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WRITE_ONCE(ads->ds_ctl0, (i->pkt_len & AR_FrameLen)
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| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
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| SM(i->txpower[0], AR_XmitPower0)
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| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
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| (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
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| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
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| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
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| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
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(i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0)));
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WRITE_ONCE(ads->ds_ctl1, ctl1);
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WRITE_ONCE(ads->ds_ctl6, ctl6);
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if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST)
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return;
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WRITE_ONCE(ads->ds_ctl4, set11nPktDurRTSCTS(i->rates, 0)
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| set11nPktDurRTSCTS(i->rates, 1));
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WRITE_ONCE(ads->ds_ctl5, set11nPktDurRTSCTS(i->rates, 2)
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| set11nPktDurRTSCTS(i->rates, 3));
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WRITE_ONCE(ads->ds_ctl7,
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set11nRateFlags(i->rates, 0) | set11nChainSel(i->rates, 0)
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| set11nRateFlags(i->rates, 1) | set11nChainSel(i->rates, 1)
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| set11nRateFlags(i->rates, 2) | set11nChainSel(i->rates, 2)
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| set11nRateFlags(i->rates, 3) | set11nChainSel(i->rates, 3)
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| SM(i->rtscts_rate, AR_RTSCTSRate));
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WRITE_ONCE(ads->ds_ctl9, SM(i->txpower[1], AR_XmitPower1));
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WRITE_ONCE(ads->ds_ctl10, SM(i->txpower[2], AR_XmitPower2));
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WRITE_ONCE(ads->ds_ctl11, SM(i->txpower[3], AR_XmitPower3));
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}
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static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
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struct ath_tx_status *ts)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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u32 status;
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status = READ_ONCE(ads->ds_txstatus9);
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if ((status & AR_TxDone) == 0)
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return -EINPROGRESS;
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ts->ts_tstamp = ads->AR_SendTimestamp;
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ts->ts_status = 0;
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ts->ts_flags = 0;
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if (status & AR_TxOpExceeded)
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||
|
|
ts->ts_status |= ATH9K_TXERR_XTXOP;
|
||
|
|
ts->tid = MS(status, AR_TxTid);
|
||
|
|
ts->ts_rateindex = MS(status, AR_FinalTxIdx);
|
||
|
|
ts->ts_seqnum = MS(status, AR_SeqNum);
|
||
|
|
|
||
|
|
status = READ_ONCE(ads->ds_txstatus0);
|
||
|
|
ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
|
||
|
|
ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
|
||
|
|
ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
|
||
|
|
if (status & AR_TxBaStatus) {
|
||
|
|
ts->ts_flags |= ATH9K_TX_BA;
|
||
|
|
ts->ba_low = ads->AR_BaBitmapLow;
|
||
|
|
ts->ba_high = ads->AR_BaBitmapHigh;
|
||
|
|
}
|
||
|
|
|
||
|
|
status = READ_ONCE(ads->ds_txstatus1);
|
||
|
|
if (status & AR_FrmXmitOK)
|
||
|
|
ts->ts_status |= ATH9K_TX_ACKED;
|
||
|
|
else {
|
||
|
|
if (status & AR_ExcessiveRetries)
|
||
|
|
ts->ts_status |= ATH9K_TXERR_XRETRY;
|
||
|
|
if (status & AR_Filtered)
|
||
|
|
ts->ts_status |= ATH9K_TXERR_FILT;
|
||
|
|
if (status & AR_FIFOUnderrun) {
|
||
|
|
ts->ts_status |= ATH9K_TXERR_FIFO;
|
||
|
|
ath9k_hw_updatetxtriglevel(ah, true);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (status & AR_TxTimerExpired)
|
||
|
|
ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
|
||
|
|
if (status & AR_DescCfgErr)
|
||
|
|
ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
|
||
|
|
if (status & AR_TxDataUnderrun) {
|
||
|
|
ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
|
||
|
|
ath9k_hw_updatetxtriglevel(ah, true);
|
||
|
|
}
|
||
|
|
if (status & AR_TxDelimUnderrun) {
|
||
|
|
ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
|
||
|
|
ath9k_hw_updatetxtriglevel(ah, true);
|
||
|
|
}
|
||
|
|
ts->ts_shortretry = MS(status, AR_RTSFailCnt);
|
||
|
|
ts->ts_longretry = MS(status, AR_DataFailCnt);
|
||
|
|
ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
|
||
|
|
|
||
|
|
status = READ_ONCE(ads->ds_txstatus5);
|
||
|
|
ts->ts_rssi = MS(status, AR_TxRSSICombined);
|
||
|
|
ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
|
||
|
|
ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
|
||
|
|
ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
|
||
|
|
|
||
|
|
ts->evm0 = ads->AR_TxEVM0;
|
||
|
|
ts->evm1 = ads->AR_TxEVM1;
|
||
|
|
ts->evm2 = ads->AR_TxEVM2;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ar9002_hw_get_duration(struct ath_hw *ah, const void *ds, int index)
|
||
|
|
{
|
||
|
|
struct ar5416_desc *ads = AR5416DESC(ds);
|
||
|
|
|
||
|
|
switch (index) {
|
||
|
|
case 0:
|
||
|
|
return MS(READ_ONCE(ads->ds_ctl4), AR_PacketDur0);
|
||
|
|
case 1:
|
||
|
|
return MS(READ_ONCE(ads->ds_ctl4), AR_PacketDur1);
|
||
|
|
case 2:
|
||
|
|
return MS(READ_ONCE(ads->ds_ctl5), AR_PacketDur2);
|
||
|
|
case 3:
|
||
|
|
return MS(READ_ONCE(ads->ds_ctl5), AR_PacketDur3);
|
||
|
|
default:
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
|
||
|
|
u32 size, u32 flags)
|
||
|
|
{
|
||
|
|
struct ar5416_desc *ads = AR5416DESC(ds);
|
||
|
|
|
||
|
|
ads->ds_ctl1 = size & AR_BufLen;
|
||
|
|
if (flags & ATH9K_RXDESC_INTREQ)
|
||
|
|
ads->ds_ctl1 |= AR_RxIntrReq;
|
||
|
|
|
||
|
|
memset(&ads->u.rx, 0, sizeof(ads->u.rx));
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
|
||
|
|
|
||
|
|
void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
|
||
|
|
{
|
||
|
|
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
||
|
|
|
||
|
|
ops->rx_enable = ar9002_hw_rx_enable;
|
||
|
|
ops->set_desc_link = ar9002_hw_set_desc_link;
|
||
|
|
ops->get_isr = ar9002_hw_get_isr;
|
||
|
|
ops->set_txdesc = ar9002_set_txdesc;
|
||
|
|
ops->proc_txdesc = ar9002_hw_proc_txdesc;
|
||
|
|
ops->get_duration = ar9002_hw_get_duration;
|
||
|
|
}
|