83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* Microchip Sparx5 Switch driver
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*
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* Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
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*/
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#ifndef __SPARX5_QOS_H__
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#define __SPARX5_QOS_H__
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#include <linux/netdevice.h>
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/* Number of Layers */
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#define SPX5_HSCH_LAYER_CNT 3
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/* Scheduling elements per layer */
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#define SPX5_HSCH_L0_SE_CNT 5040
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#define SPX5_HSCH_L1_SE_CNT 64
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#define SPX5_HSCH_L2_SE_CNT 64
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/* Calculate Layer 0 Scheduler Element when using normal hierarchy */
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#define SPX5_HSCH_L0_GET_IDX(port, queue) ((64 * (port)) + (8 * (queue)))
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/* Number of leak groups */
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#define SPX5_HSCH_LEAK_GRP_CNT 4
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/* Scheduler modes */
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#define SPX5_SE_MODE_LINERATE 0
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#define SPX5_SE_MODE_DATARATE 1
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/* Rate and burst */
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#define SPX5_SE_RATE_MAX 262143
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#define SPX5_SE_BURST_MAX 127
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#define SPX5_SE_RATE_MIN 1
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#define SPX5_SE_BURST_MIN 1
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#define SPX5_SE_BURST_UNIT 4096
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/* Dwrr */
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#define SPX5_DWRR_COST_MAX 63
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struct sparx5_shaper {
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u32 mode;
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u32 rate;
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u32 burst;
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};
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struct sparx5_lg {
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u32 max_rate;
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u32 resolution;
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u32 leak_time;
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u32 max_ses;
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};
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struct sparx5_layer {
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struct sparx5_lg leak_groups[SPX5_HSCH_LEAK_GRP_CNT];
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};
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struct sparx5_dwrr {
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u32 count; /* Number of inputs running dwrr */
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u8 cost[SPX5_PRIOS];
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};
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int sparx5_qos_init(struct sparx5 *sparx5);
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/* Multi-Queue Priority */
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int sparx5_tc_mqprio_add(struct net_device *ndev, u8 num_tc);
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int sparx5_tc_mqprio_del(struct net_device *ndev);
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/* Token Bucket Filter */
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struct tc_tbf_qopt_offload_replace_params;
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int sparx5_tc_tbf_add(struct sparx5_port *port,
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struct tc_tbf_qopt_offload_replace_params *params,
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u32 layer, u32 idx);
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int sparx5_tc_tbf_del(struct sparx5_port *port, u32 layer, u32 idx);
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/* Enhanced Transmission Selection */
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struct tc_ets_qopt_offload_replace_params;
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int sparx5_tc_ets_add(struct sparx5_port *port,
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struct tc_ets_qopt_offload_replace_params *params);
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int sparx5_tc_ets_del(struct sparx5_port *port);
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#endif /* __SPARX5_QOS_H__ */
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