811 lines
22 KiB
C
811 lines
22 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2007 - 2018 Intel Corporation. */
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/* Linux PRO/1000 Ethernet Driver main header file */
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#ifndef _IGB_H_
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#define _IGB_H_
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#include "e1000_mac.h"
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#include "e1000_82575.h"
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#include <linux/timecounter.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/bitops.h>
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#include <linux/if_vlan.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/pci.h>
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#include <linux/mdio.h>
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#include <net/xdp.h>
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struct igb_adapter;
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#define E1000_PCS_CFG_IGN_SD 1
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/* Interrupt defines */
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#define IGB_START_ITR 648 /* ~6000 ints/sec */
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#define IGB_4K_ITR 980
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#define IGB_20K_ITR 196
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#define IGB_70K_ITR 56
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/* TX/RX descriptor defines */
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#define IGB_DEFAULT_TXD 256
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#define IGB_DEFAULT_TX_WORK 128
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#define IGB_MIN_TXD 64
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#define IGB_MAX_TXD 4096
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#define IGB_DEFAULT_RXD 256
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#define IGB_MIN_RXD 64
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#define IGB_MAX_RXD 4096
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#define IGB_DEFAULT_ITR 3 /* dynamic */
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#define IGB_MAX_ITR_USECS 10000
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#define IGB_MIN_ITR_USECS 10
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#define NON_Q_VECTORS 1
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#define MAX_Q_VECTORS 8
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#define MAX_MSIX_ENTRIES 10
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/* Transmit and receive queues */
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#define IGB_MAX_RX_QUEUES 8
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#define IGB_MAX_RX_QUEUES_82575 4
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#define IGB_MAX_RX_QUEUES_I211 2
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#define IGB_MAX_TX_QUEUES 8
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#define IGB_MAX_VF_MC_ENTRIES 30
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#define IGB_MAX_VF_FUNCTIONS 8
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#define IGB_MAX_VFTA_ENTRIES 128
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#define IGB_82576_VF_DEV_ID 0x10CA
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#define IGB_I350_VF_DEV_ID 0x1520
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/* NVM version defines */
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#define IGB_MAJOR_MASK 0xF000
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#define IGB_MINOR_MASK 0x0FF0
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#define IGB_BUILD_MASK 0x000F
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#define IGB_COMB_VER_MASK 0x00FF
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#define IGB_MAJOR_SHIFT 12
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#define IGB_MINOR_SHIFT 4
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#define IGB_COMB_VER_SHFT 8
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#define IGB_NVM_VER_INVALID 0xFFFF
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#define IGB_ETRACK_SHIFT 16
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#define NVM_ETRACK_WORD 0x0042
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#define NVM_COMB_VER_OFF 0x0083
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#define NVM_COMB_VER_PTR 0x003d
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/* Transmit and receive latency (for PTP timestamps) */
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#define IGB_I210_TX_LATENCY_10 9542
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#define IGB_I210_TX_LATENCY_100 1024
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#define IGB_I210_TX_LATENCY_1000 178
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#define IGB_I210_RX_LATENCY_10 20662
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#define IGB_I210_RX_LATENCY_100 2213
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#define IGB_I210_RX_LATENCY_1000 448
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/* XDP */
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#define IGB_XDP_PASS 0
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#define IGB_XDP_CONSUMED BIT(0)
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#define IGB_XDP_TX BIT(1)
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#define IGB_XDP_REDIR BIT(2)
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struct vf_data_storage {
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unsigned char vf_mac_addresses[ETH_ALEN];
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u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
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u16 num_vf_mc_hashes;
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u32 flags;
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unsigned long last_nack;
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u16 pf_vlan; /* When set, guest VLAN config not allowed. */
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u16 pf_qos;
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u16 tx_rate;
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bool spoofchk_enabled;
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bool trusted;
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};
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/* Number of unicast MAC filters reserved for the PF in the RAR registers */
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#define IGB_PF_MAC_FILTERS_RESERVED 3
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struct vf_mac_filter {
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struct list_head l;
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int vf;
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bool free;
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u8 vf_mac[ETH_ALEN];
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};
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#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
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#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
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#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
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#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
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/* RX descriptor control thresholds.
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* PTHRESH - MAC will consider prefetch if it has fewer than this number of
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* descriptors available in its onboard memory.
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* Setting this to 0 disables RX descriptor prefetch.
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* HTHRESH - MAC will only prefetch if there are at least this many descriptors
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* available in host memory.
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* If PTHRESH is 0, this should also be 0.
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* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
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* descriptors until either it has this many to write back, or the
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* ITR timer expires.
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*/
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#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
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#define IGB_RX_HTHRESH 8
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#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
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#define IGB_TX_HTHRESH 1
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#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
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(adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
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#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
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(adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
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/* this is the size past which hardware will drop packets when setting LPE=0 */
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#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
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#define IGB_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
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/* Supported Rx Buffer Sizes */
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#define IGB_RXBUFFER_256 256
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#define IGB_RXBUFFER_1536 1536
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#define IGB_RXBUFFER_2048 2048
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#define IGB_RXBUFFER_3072 3072
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#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
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#define IGB_TS_HDR_LEN 16
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/* Attempt to maximize the headroom available for incoming frames. We
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* use a 2K buffer for receives and need 1536/1534 to store the data for
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* the frame. This leaves us with 512 bytes of room. From that we need
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* to deduct the space needed for the shared info and the padding needed
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* to IP align the frame.
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*
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* Note: For cache line sizes 256 or larger this value is going to end
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* up negative. In these cases we should fall back to the 3K
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* buffers.
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*/
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#if (PAGE_SIZE < 8192)
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#define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_1536 - NET_IP_ALIGN)
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#define IGB_2K_TOO_SMALL_WITH_PADDING \
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((NET_SKB_PAD + IGB_TS_HDR_LEN + IGB_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048))
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static inline int igb_compute_pad(int rx_buf_len)
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{
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int page_size, pad_size;
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page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
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pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
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return pad_size;
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}
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static inline int igb_skb_pad(void)
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{
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int rx_buf_len;
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/* If a 2K buffer cannot handle a standard Ethernet frame then
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* optimize padding for a 3K buffer instead of a 1.5K buffer.
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*
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* For a 3K buffer we need to add enough padding to allow for
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* tailroom due to NET_IP_ALIGN possibly shifting us out of
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* cache-line alignment.
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*/
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if (IGB_2K_TOO_SMALL_WITH_PADDING)
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rx_buf_len = IGB_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
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else
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rx_buf_len = IGB_RXBUFFER_1536;
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/* if needed make room for NET_IP_ALIGN */
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rx_buf_len -= NET_IP_ALIGN;
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return igb_compute_pad(rx_buf_len);
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}
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#define IGB_SKB_PAD igb_skb_pad()
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#else
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#define IGB_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
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#endif
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define IGB_RX_DMA_ATTR \
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(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
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#define AUTO_ALL_MODES 0
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#define IGB_EEPROM_APME 0x0400
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#ifndef IGB_MASTER_SLAVE
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/* Switch to override PHY master/slave setting */
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#define IGB_MASTER_SLAVE e1000_ms_hw_default
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#endif
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#define IGB_MNG_VLAN_NONE -1
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enum igb_tx_flags {
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/* cmd_type flags */
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IGB_TX_FLAGS_VLAN = 0x01,
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IGB_TX_FLAGS_TSO = 0x02,
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IGB_TX_FLAGS_TSTAMP = 0x04,
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/* olinfo flags */
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IGB_TX_FLAGS_IPV4 = 0x10,
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IGB_TX_FLAGS_CSUM = 0x20,
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};
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/* VLAN info */
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#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
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#define IGB_TX_FLAGS_VLAN_SHIFT 16
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/* The largest size we can write to the descriptor is 65535. In order to
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* maintain a power of two alignment we have to limit ourselves to 32K.
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*/
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#define IGB_MAX_TXD_PWR 15
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#define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR)
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/* Tx Descriptors needed, worst case */
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#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
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#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
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/* EEPROM byte offsets */
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#define IGB_SFF_8472_SWAP 0x5C
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#define IGB_SFF_8472_COMP 0x5E
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/* Bitmasks */
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#define IGB_SFF_ADDRESSING_MODE 0x4
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#define IGB_SFF_8472_UNSUP 0x00
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/* TX resources are shared between XDP and netstack
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* and we need to tag the buffer type to distinguish them
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*/
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enum igb_tx_buf_type {
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IGB_TYPE_SKB = 0,
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IGB_TYPE_XDP,
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};
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer
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*/
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struct igb_tx_buffer {
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union e1000_adv_tx_desc *next_to_watch;
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unsigned long time_stamp;
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enum igb_tx_buf_type type;
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union {
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struct sk_buff *skb;
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struct xdp_frame *xdpf;
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};
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unsigned int bytecount;
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u16 gso_segs;
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__be16 protocol;
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DEFINE_DMA_UNMAP_ADDR(dma);
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DEFINE_DMA_UNMAP_LEN(len);
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u32 tx_flags;
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};
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struct igb_rx_buffer {
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dma_addr_t dma;
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struct page *page;
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#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
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__u32 page_offset;
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#else
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__u16 page_offset;
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#endif
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__u16 pagecnt_bias;
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};
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struct igb_tx_queue_stats {
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u64 packets;
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u64 bytes;
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u64 restart_queue;
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u64 restart_queue2;
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};
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struct igb_rx_queue_stats {
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u64 packets;
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u64 bytes;
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u64 drops;
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u64 csum_err;
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u64 alloc_failed;
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};
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struct igb_ring_container {
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struct igb_ring *ring; /* pointer to linked list of rings */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 work_limit; /* total work allowed per interrupt */
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u8 count; /* total number of rings in vector */
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u8 itr; /* current ITR setting for ring */
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};
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struct igb_ring {
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struct igb_q_vector *q_vector; /* backlink to q_vector */
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struct net_device *netdev; /* back pointer to net_device */
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struct bpf_prog *xdp_prog;
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struct device *dev; /* device pointer for dma mapping */
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union { /* array of buffer info structs */
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struct igb_tx_buffer *tx_buffer_info;
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struct igb_rx_buffer *rx_buffer_info;
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};
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void *desc; /* descriptor ring memory */
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unsigned long flags; /* ring specific flags */
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void __iomem *tail; /* pointer to ring tail register */
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dma_addr_t dma; /* phys address of the ring */
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unsigned int size; /* length of desc. ring in bytes */
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u16 count; /* number of desc. in the ring */
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u8 queue_index; /* logical index of the ring*/
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u8 reg_idx; /* physical index of the ring */
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bool launchtime_enable; /* true if LaunchTime is enabled */
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bool cbs_enable; /* indicates if CBS is enabled */
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s32 idleslope; /* idleSlope in kbps */
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s32 sendslope; /* sendSlope in kbps */
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s32 hicredit; /* hiCredit in bytes */
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s32 locredit; /* loCredit in bytes */
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/* everything past this point are written often */
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u16 next_to_clean;
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u16 next_to_use;
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u16 next_to_alloc;
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union {
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/* TX */
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struct {
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struct igb_tx_queue_stats tx_stats;
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|
|
struct u64_stats_sync tx_syncp;
|
||
|
|
struct u64_stats_sync tx_syncp2;
|
||
|
|
};
|
||
|
|
/* RX */
|
||
|
|
struct {
|
||
|
|
struct sk_buff *skb;
|
||
|
|
struct igb_rx_queue_stats rx_stats;
|
||
|
|
struct u64_stats_sync rx_syncp;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
struct xdp_rxq_info xdp_rxq;
|
||
|
|
} ____cacheline_internodealigned_in_smp;
|
||
|
|
|
||
|
|
struct igb_q_vector {
|
||
|
|
struct igb_adapter *adapter; /* backlink */
|
||
|
|
int cpu; /* CPU for DCA */
|
||
|
|
u32 eims_value; /* EIMS mask value */
|
||
|
|
|
||
|
|
u16 itr_val;
|
||
|
|
u8 set_itr;
|
||
|
|
void __iomem *itr_register;
|
||
|
|
|
||
|
|
struct igb_ring_container rx, tx;
|
||
|
|
|
||
|
|
struct napi_struct napi;
|
||
|
|
struct rcu_head rcu; /* to avoid race with update stats on free */
|
||
|
|
char name[IFNAMSIZ + 9];
|
||
|
|
|
||
|
|
/* for dynamic allocation of rings associated with this q_vector */
|
||
|
|
struct igb_ring ring[] ____cacheline_internodealigned_in_smp;
|
||
|
|
};
|
||
|
|
|
||
|
|
enum e1000_ring_flags_t {
|
||
|
|
IGB_RING_FLAG_RX_3K_BUFFER,
|
||
|
|
IGB_RING_FLAG_RX_BUILD_SKB_ENABLED,
|
||
|
|
IGB_RING_FLAG_RX_SCTP_CSUM,
|
||
|
|
IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
|
||
|
|
IGB_RING_FLAG_TX_CTX_IDX,
|
||
|
|
IGB_RING_FLAG_TX_DETECT_HANG
|
||
|
|
};
|
||
|
|
|
||
|
|
#define ring_uses_large_buffer(ring) \
|
||
|
|
test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
|
||
|
|
#define set_ring_uses_large_buffer(ring) \
|
||
|
|
set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
|
||
|
|
#define clear_ring_uses_large_buffer(ring) \
|
||
|
|
clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
|
||
|
|
|
||
|
|
#define ring_uses_build_skb(ring) \
|
||
|
|
test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
|
||
|
|
#define set_ring_build_skb_enabled(ring) \
|
||
|
|
set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
|
||
|
|
#define clear_ring_build_skb_enabled(ring) \
|
||
|
|
clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
|
||
|
|
|
||
|
|
static inline unsigned int igb_rx_bufsz(struct igb_ring *ring)
|
||
|
|
{
|
||
|
|
#if (PAGE_SIZE < 8192)
|
||
|
|
if (ring_uses_large_buffer(ring))
|
||
|
|
return IGB_RXBUFFER_3072;
|
||
|
|
|
||
|
|
if (ring_uses_build_skb(ring))
|
||
|
|
return IGB_MAX_FRAME_BUILD_SKB;
|
||
|
|
#endif
|
||
|
|
return IGB_RXBUFFER_2048;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned int igb_rx_pg_order(struct igb_ring *ring)
|
||
|
|
{
|
||
|
|
#if (PAGE_SIZE < 8192)
|
||
|
|
if (ring_uses_large_buffer(ring))
|
||
|
|
return 1;
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring))
|
||
|
|
|
||
|
|
#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
|
||
|
|
|
||
|
|
#define IGB_RX_DESC(R, i) \
|
||
|
|
(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
|
||
|
|
#define IGB_TX_DESC(R, i) \
|
||
|
|
(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
|
||
|
|
#define IGB_TX_CTXTDESC(R, i) \
|
||
|
|
(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
|
||
|
|
|
||
|
|
/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
|
||
|
|
static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
|
||
|
|
const u32 stat_err_bits)
|
||
|
|
{
|
||
|
|
return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* igb_desc_unused - calculate if we have unused descriptors */
|
||
|
|
static inline int igb_desc_unused(struct igb_ring *ring)
|
||
|
|
{
|
||
|
|
if (ring->next_to_clean > ring->next_to_use)
|
||
|
|
return ring->next_to_clean - ring->next_to_use - 1;
|
||
|
|
|
||
|
|
return ring->count + ring->next_to_clean - ring->next_to_use - 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_IGB_HWMON
|
||
|
|
|
||
|
|
#define IGB_HWMON_TYPE_LOC 0
|
||
|
|
#define IGB_HWMON_TYPE_TEMP 1
|
||
|
|
#define IGB_HWMON_TYPE_CAUTION 2
|
||
|
|
#define IGB_HWMON_TYPE_MAX 3
|
||
|
|
|
||
|
|
struct hwmon_attr {
|
||
|
|
struct device_attribute dev_attr;
|
||
|
|
struct e1000_hw *hw;
|
||
|
|
struct e1000_thermal_diode_data *sensor;
|
||
|
|
char name[12];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct hwmon_buff {
|
||
|
|
struct attribute_group group;
|
||
|
|
const struct attribute_group *groups[2];
|
||
|
|
struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
|
||
|
|
struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
|
||
|
|
unsigned int n_hwmon;
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* The number of L2 ether-type filter registers, Index 3 is reserved
|
||
|
|
* for PTP 1588 timestamp
|
||
|
|
*/
|
||
|
|
#define MAX_ETYPE_FILTER (4 - 1)
|
||
|
|
/* ETQF filter list: one static filter per filter consumer. This is
|
||
|
|
* to avoid filter collisions later. Add new filters here!!
|
||
|
|
*
|
||
|
|
* Current filters: Filter 3
|
||
|
|
*/
|
||
|
|
#define IGB_ETQF_FILTER_1588 3
|
||
|
|
|
||
|
|
#define IGB_N_EXTTS 2
|
||
|
|
#define IGB_N_PEROUT 2
|
||
|
|
#define IGB_N_SDP 4
|
||
|
|
#define IGB_RETA_SIZE 128
|
||
|
|
|
||
|
|
enum igb_filter_match_flags {
|
||
|
|
IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
|
||
|
|
IGB_FILTER_FLAG_VLAN_TCI = 0x2,
|
||
|
|
IGB_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
|
||
|
|
IGB_FILTER_FLAG_DST_MAC_ADDR = 0x8,
|
||
|
|
};
|
||
|
|
|
||
|
|
#define IGB_MAX_RXNFC_FILTERS 16
|
||
|
|
|
||
|
|
/* RX network flow classification data structure */
|
||
|
|
struct igb_nfc_input {
|
||
|
|
/* Byte layout in order, all values with MSB first:
|
||
|
|
* match_flags - 1 byte
|
||
|
|
* etype - 2 bytes
|
||
|
|
* vlan_tci - 2 bytes
|
||
|
|
*/
|
||
|
|
u8 match_flags;
|
||
|
|
__be16 etype;
|
||
|
|
__be16 vlan_tci;
|
||
|
|
u8 src_addr[ETH_ALEN];
|
||
|
|
u8 dst_addr[ETH_ALEN];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct igb_nfc_filter {
|
||
|
|
struct hlist_node nfc_node;
|
||
|
|
struct igb_nfc_input filter;
|
||
|
|
unsigned long cookie;
|
||
|
|
u16 etype_reg_index;
|
||
|
|
u16 sw_idx;
|
||
|
|
u16 action;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct igb_mac_addr {
|
||
|
|
u8 addr[ETH_ALEN];
|
||
|
|
u8 queue;
|
||
|
|
u8 state; /* bitmask */
|
||
|
|
};
|
||
|
|
|
||
|
|
#define IGB_MAC_STATE_DEFAULT 0x1
|
||
|
|
#define IGB_MAC_STATE_IN_USE 0x2
|
||
|
|
#define IGB_MAC_STATE_SRC_ADDR 0x4
|
||
|
|
#define IGB_MAC_STATE_QUEUE_STEERING 0x8
|
||
|
|
|
||
|
|
/* board specific private data structure */
|
||
|
|
struct igb_adapter {
|
||
|
|
unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
|
||
|
|
|
||
|
|
struct net_device *netdev;
|
||
|
|
struct bpf_prog *xdp_prog;
|
||
|
|
|
||
|
|
unsigned long state;
|
||
|
|
unsigned int flags;
|
||
|
|
|
||
|
|
unsigned int num_q_vectors;
|
||
|
|
struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
|
||
|
|
|
||
|
|
/* Interrupt Throttle Rate */
|
||
|
|
u32 rx_itr_setting;
|
||
|
|
u32 tx_itr_setting;
|
||
|
|
u16 tx_itr;
|
||
|
|
u16 rx_itr;
|
||
|
|
|
||
|
|
/* TX */
|
||
|
|
u16 tx_work_limit;
|
||
|
|
u32 tx_timeout_count;
|
||
|
|
int num_tx_queues;
|
||
|
|
struct igb_ring *tx_ring[16];
|
||
|
|
|
||
|
|
/* RX */
|
||
|
|
int num_rx_queues;
|
||
|
|
struct igb_ring *rx_ring[16];
|
||
|
|
|
||
|
|
u32 max_frame_size;
|
||
|
|
u32 min_frame_size;
|
||
|
|
|
||
|
|
struct timer_list watchdog_timer;
|
||
|
|
struct timer_list phy_info_timer;
|
||
|
|
|
||
|
|
u16 mng_vlan_id;
|
||
|
|
u32 bd_number;
|
||
|
|
u32 wol;
|
||
|
|
u32 en_mng_pt;
|
||
|
|
u16 link_speed;
|
||
|
|
u16 link_duplex;
|
||
|
|
|
||
|
|
u8 __iomem *io_addr; /* Mainly for iounmap use */
|
||
|
|
|
||
|
|
struct work_struct reset_task;
|
||
|
|
struct work_struct watchdog_task;
|
||
|
|
bool fc_autoneg;
|
||
|
|
u8 tx_timeout_factor;
|
||
|
|
struct timer_list blink_timer;
|
||
|
|
unsigned long led_status;
|
||
|
|
|
||
|
|
/* OS defined structs */
|
||
|
|
struct pci_dev *pdev;
|
||
|
|
|
||
|
|
spinlock_t stats64_lock;
|
||
|
|
struct rtnl_link_stats64 stats64;
|
||
|
|
|
||
|
|
/* structs defined in e1000_hw.h */
|
||
|
|
struct e1000_hw hw;
|
||
|
|
struct e1000_hw_stats stats;
|
||
|
|
struct e1000_phy_info phy_info;
|
||
|
|
|
||
|
|
u32 test_icr;
|
||
|
|
struct igb_ring test_tx_ring;
|
||
|
|
struct igb_ring test_rx_ring;
|
||
|
|
|
||
|
|
int msg_enable;
|
||
|
|
|
||
|
|
struct igb_q_vector *q_vector[MAX_Q_VECTORS];
|
||
|
|
u32 eims_enable_mask;
|
||
|
|
u32 eims_other;
|
||
|
|
|
||
|
|
/* to not mess up cache alignment, always add to the bottom */
|
||
|
|
u16 tx_ring_count;
|
||
|
|
u16 rx_ring_count;
|
||
|
|
unsigned int vfs_allocated_count;
|
||
|
|
struct vf_data_storage *vf_data;
|
||
|
|
int vf_rate_link_speed;
|
||
|
|
u32 rss_queues;
|
||
|
|
u32 wvbr;
|
||
|
|
u32 *shadow_vfta;
|
||
|
|
|
||
|
|
struct ptp_clock *ptp_clock;
|
||
|
|
struct ptp_clock_info ptp_caps;
|
||
|
|
struct delayed_work ptp_overflow_work;
|
||
|
|
struct work_struct ptp_tx_work;
|
||
|
|
struct sk_buff *ptp_tx_skb;
|
||
|
|
struct hwtstamp_config tstamp_config;
|
||
|
|
unsigned long ptp_tx_start;
|
||
|
|
unsigned long last_rx_ptp_check;
|
||
|
|
unsigned long last_rx_timestamp;
|
||
|
|
unsigned int ptp_flags;
|
||
|
|
spinlock_t tmreg_lock;
|
||
|
|
struct cyclecounter cc;
|
||
|
|
struct timecounter tc;
|
||
|
|
u32 tx_hwtstamp_timeouts;
|
||
|
|
u32 tx_hwtstamp_skipped;
|
||
|
|
u32 rx_hwtstamp_cleared;
|
||
|
|
bool pps_sys_wrap_on;
|
||
|
|
|
||
|
|
struct ptp_pin_desc sdp_config[IGB_N_SDP];
|
||
|
|
struct {
|
||
|
|
struct timespec64 start;
|
||
|
|
struct timespec64 period;
|
||
|
|
} perout[IGB_N_PEROUT];
|
||
|
|
|
||
|
|
char fw_version[32];
|
||
|
|
#ifdef CONFIG_IGB_HWMON
|
||
|
|
struct hwmon_buff *igb_hwmon_buff;
|
||
|
|
bool ets;
|
||
|
|
#endif
|
||
|
|
struct i2c_algo_bit_data i2c_algo;
|
||
|
|
struct i2c_adapter i2c_adap;
|
||
|
|
struct i2c_client *i2c_client;
|
||
|
|
u32 rss_indir_tbl_init;
|
||
|
|
u8 rss_indir_tbl[IGB_RETA_SIZE];
|
||
|
|
|
||
|
|
unsigned long link_check_timeout;
|
||
|
|
int copper_tries;
|
||
|
|
struct e1000_info ei;
|
||
|
|
u16 eee_advert;
|
||
|
|
|
||
|
|
/* RX network flow classification support */
|
||
|
|
struct hlist_head nfc_filter_list;
|
||
|
|
struct hlist_head cls_flower_list;
|
||
|
|
unsigned int nfc_filter_count;
|
||
|
|
/* lock for RX network flow classification filter */
|
||
|
|
spinlock_t nfc_lock;
|
||
|
|
bool etype_bitmap[MAX_ETYPE_FILTER];
|
||
|
|
|
||
|
|
struct igb_mac_addr *mac_table;
|
||
|
|
struct vf_mac_filter vf_macs;
|
||
|
|
struct vf_mac_filter *vf_mac_list;
|
||
|
|
/* lock for VF resources */
|
||
|
|
spinlock_t vfs_lock;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* flags controlling PTP/1588 function */
|
||
|
|
#define IGB_PTP_ENABLED BIT(0)
|
||
|
|
#define IGB_PTP_OVERFLOW_CHECK BIT(1)
|
||
|
|
|
||
|
|
#define IGB_FLAG_HAS_MSI BIT(0)
|
||
|
|
#define IGB_FLAG_DCA_ENABLED BIT(1)
|
||
|
|
#define IGB_FLAG_QUAD_PORT_A BIT(2)
|
||
|
|
#define IGB_FLAG_QUEUE_PAIRS BIT(3)
|
||
|
|
#define IGB_FLAG_DMAC BIT(4)
|
||
|
|
#define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
|
||
|
|
#define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
|
||
|
|
#define IGB_FLAG_WOL_SUPPORTED BIT(8)
|
||
|
|
#define IGB_FLAG_NEED_LINK_UPDATE BIT(9)
|
||
|
|
#define IGB_FLAG_MEDIA_RESET BIT(10)
|
||
|
|
#define IGB_FLAG_MAS_CAPABLE BIT(11)
|
||
|
|
#define IGB_FLAG_MAS_ENABLE BIT(12)
|
||
|
|
#define IGB_FLAG_HAS_MSIX BIT(13)
|
||
|
|
#define IGB_FLAG_EEE BIT(14)
|
||
|
|
#define IGB_FLAG_VLAN_PROMISC BIT(15)
|
||
|
|
#define IGB_FLAG_RX_LEGACY BIT(16)
|
||
|
|
#define IGB_FLAG_FQTSS BIT(17)
|
||
|
|
|
||
|
|
/* Media Auto Sense */
|
||
|
|
#define IGB_MAS_ENABLE_0 0X0001
|
||
|
|
#define IGB_MAS_ENABLE_1 0X0002
|
||
|
|
#define IGB_MAS_ENABLE_2 0X0004
|
||
|
|
#define IGB_MAS_ENABLE_3 0X0008
|
||
|
|
|
||
|
|
/* DMA Coalescing defines */
|
||
|
|
#define IGB_MIN_TXPBSIZE 20408
|
||
|
|
#define IGB_TX_BUF_4096 4096
|
||
|
|
#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
|
||
|
|
|
||
|
|
#define IGB_82576_TSYNC_SHIFT 19
|
||
|
|
enum e1000_state_t {
|
||
|
|
__IGB_TESTING,
|
||
|
|
__IGB_RESETTING,
|
||
|
|
__IGB_DOWN,
|
||
|
|
__IGB_PTP_TX_IN_PROGRESS,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum igb_boards {
|
||
|
|
board_82575,
|
||
|
|
};
|
||
|
|
|
||
|
|
extern char igb_driver_name[];
|
||
|
|
|
||
|
|
int igb_xmit_xdp_ring(struct igb_adapter *adapter,
|
||
|
|
struct igb_ring *ring,
|
||
|
|
struct xdp_frame *xdpf);
|
||
|
|
int igb_open(struct net_device *netdev);
|
||
|
|
int igb_close(struct net_device *netdev);
|
||
|
|
int igb_up(struct igb_adapter *);
|
||
|
|
void igb_down(struct igb_adapter *);
|
||
|
|
void igb_reinit_locked(struct igb_adapter *);
|
||
|
|
void igb_reset(struct igb_adapter *);
|
||
|
|
int igb_reinit_queues(struct igb_adapter *);
|
||
|
|
void igb_write_rss_indir_tbl(struct igb_adapter *);
|
||
|
|
int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
|
||
|
|
int igb_setup_tx_resources(struct igb_ring *);
|
||
|
|
int igb_setup_rx_resources(struct igb_ring *);
|
||
|
|
void igb_free_tx_resources(struct igb_ring *);
|
||
|
|
void igb_free_rx_resources(struct igb_ring *);
|
||
|
|
void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
|
||
|
|
void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
|
||
|
|
void igb_setup_tctl(struct igb_adapter *);
|
||
|
|
void igb_setup_rctl(struct igb_adapter *);
|
||
|
|
void igb_setup_srrctl(struct igb_adapter *, struct igb_ring *);
|
||
|
|
netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
|
||
|
|
void igb_alloc_rx_buffers(struct igb_ring *, u16);
|
||
|
|
void igb_update_stats(struct igb_adapter *);
|
||
|
|
bool igb_has_link(struct igb_adapter *adapter);
|
||
|
|
void igb_set_ethtool_ops(struct net_device *);
|
||
|
|
void igb_power_up_link(struct igb_adapter *);
|
||
|
|
void igb_set_fw_version(struct igb_adapter *);
|
||
|
|
void igb_ptp_init(struct igb_adapter *adapter);
|
||
|
|
void igb_ptp_stop(struct igb_adapter *adapter);
|
||
|
|
void igb_ptp_reset(struct igb_adapter *adapter);
|
||
|
|
void igb_ptp_suspend(struct igb_adapter *adapter);
|
||
|
|
void igb_ptp_rx_hang(struct igb_adapter *adapter);
|
||
|
|
void igb_ptp_tx_hang(struct igb_adapter *adapter);
|
||
|
|
void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
|
||
|
|
int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
|
||
|
|
ktime_t *timestamp);
|
||
|
|
int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
|
||
|
|
int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
|
||
|
|
void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
|
||
|
|
unsigned int igb_get_max_rss_queues(struct igb_adapter *);
|
||
|
|
#ifdef CONFIG_IGB_HWMON
|
||
|
|
void igb_sysfs_exit(struct igb_adapter *adapter);
|
||
|
|
int igb_sysfs_init(struct igb_adapter *adapter);
|
||
|
|
#endif
|
||
|
|
static inline s32 igb_reset_phy(struct e1000_hw *hw)
|
||
|
|
{
|
||
|
|
if (hw->phy.ops.reset)
|
||
|
|
return hw->phy.ops.reset(hw);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
|
||
|
|
{
|
||
|
|
if (hw->phy.ops.read_reg)
|
||
|
|
return hw->phy.ops.read_reg(hw, offset, data);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
|
||
|
|
{
|
||
|
|
if (hw->phy.ops.write_reg)
|
||
|
|
return hw->phy.ops.write_reg(hw, offset, data);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline s32 igb_get_phy_info(struct e1000_hw *hw)
|
||
|
|
{
|
||
|
|
if (hw->phy.ops.get_phy_info)
|
||
|
|
return hw->phy.ops.get_phy_info(hw);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
|
||
|
|
{
|
||
|
|
return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
|
||
|
|
}
|
||
|
|
|
||
|
|
int igb_add_filter(struct igb_adapter *adapter,
|
||
|
|
struct igb_nfc_filter *input);
|
||
|
|
int igb_erase_filter(struct igb_adapter *adapter,
|
||
|
|
struct igb_nfc_filter *input);
|
||
|
|
|
||
|
|
int igb_add_mac_steering_filter(struct igb_adapter *adapter,
|
||
|
|
const u8 *addr, u8 queue, u8 flags);
|
||
|
|
int igb_del_mac_steering_filter(struct igb_adapter *adapter,
|
||
|
|
const u8 *addr, u8 queue, u8 flags);
|
||
|
|
|
||
|
|
#endif /* _IGB_H_ */
|