359 lines
11 KiB
C
359 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2019-2022 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef GAUDIP_H_
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#define GAUDIP_H_
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#include <uapi/misc/habanalabs.h>
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#include "../common/habanalabs.h"
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#include "../include/common/hl_boot_if.h"
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#include "../include/gaudi/gaudi_packets.h"
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#include "../include/gaudi/gaudi.h"
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#include "../include/gaudi/gaudi_async_events.h"
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#include "../include/gaudi/gaudi_fw_if.h"
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#define NUMBER_OF_EXT_HW_QUEUES 8
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#define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES
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#define NUMBER_OF_CPU_HW_QUEUES 1
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#define NUMBER_OF_INT_HW_QUEUES 100
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#define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
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NUMBER_OF_CPU_HW_QUEUES + \
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NUMBER_OF_INT_HW_QUEUES)
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/* 10 NIC QMANs, DMA5 QMAN, TPC7 QMAN */
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#define NUMBER_OF_COLLECTIVE_QUEUES 12
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#define NUMBER_OF_SOBS_IN_GRP 11
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/*
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* Number of MSI interrupts IDS:
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* Each completion queue has 1 ID
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* The event queue has 1 ID
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*/
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#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + \
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NUMBER_OF_CPU_HW_QUEUES)
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#define GAUDI_STREAM_MASTER_ARR_SIZE 8
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#if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES)
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#error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES"
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#endif
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#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
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#define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */
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#define MAX_POWER_DEFAULT_PCI 200000 /* 200W */
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#define MAX_POWER_DEFAULT_PMC 350000 /* 350W */
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#define DC_POWER_DEFAULT_PCI 60000 /* 60W */
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#define DC_POWER_DEFAULT_PMC 60000 /* 60W */
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#define DC_POWER_DEFAULT_PMC_SEC 97000 /* 97W */
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#define GAUDI_CPU_TIMEOUT_USEC 30000000 /* 30s */
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#define TPC_ENABLED_MASK 0xFF
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#define GAUDI_HBM_SIZE_32GB 0x800000000ull
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#define GAUDI_HBM_DEVICES 4
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#define GAUDI_HBM_CHANNELS 8
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#define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE)
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#define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE)
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#define DMA_MAX_TRANSFER_SIZE U32_MAX
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#define GAUDI_DEFAULT_CARD_NAME "HL205"
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#define GAUDI_MAX_PENDING_CS SZ_16K
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#if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS)
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#error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1"
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#endif
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#define PCI_DMA_NUMBER_OF_CHNLS 2
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#define HBM_DMA_NUMBER_OF_CHNLS 6
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#define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \
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HBM_DMA_NUMBER_OF_CHNLS)
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#define MME_NUMBER_OF_SLAVE_ENGINES 2
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#define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \
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MME_NUMBER_OF_SLAVE_ENGINES)
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#define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \
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QMAN_STREAMS)
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#define QMAN_STREAMS 4
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#define PQ_FETCHER_CACHE_SIZE 8
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#define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE)
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#define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE)
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#define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE)
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#define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE)
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#define NIC_ENGINE_QMAN_OFFSET (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
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#define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE)
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#define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE)
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#define QMAN_LDMA_SRC_OFFSET (mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0)
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#define QMAN_LDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
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#define QMAN_LDMA_SIZE_OFFSET (mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0)
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#define QMAN_CPDMA_SRC_OFFSET (mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0)
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#define QMAN_CPDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
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#define QMAN_CPDMA_SIZE_OFFSET (mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0)
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#define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE)
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#define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE)
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#define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE)
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#define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
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#define NUM_OF_SOB_IN_BLOCK \
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(((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
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mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
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#define NUM_OF_MONITORS_IN_BLOCK \
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(((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \
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mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
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#define MONITOR_MAX_SOBS 8
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/* DRAM Memory Map */
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#define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */
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#define MMU_PAGE_TABLES_SIZE 0x0BF00000 /* 191MB */
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#define MMU_CACHE_MNG_SIZE 0x00100000 /* 1MB */
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#define RESERVED 0x04000000 /* 64MB */
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#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
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#define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
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#define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE)
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#define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\
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RESERVED)
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#define DRAM_BASE_ADDR_USER 0x20000000
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#if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
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#error "Driver must reserve no more than 512MB"
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#endif
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/* Internal QMANs PQ sizes */
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#define MME_QMAN_LENGTH 1024
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#define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
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#define HBM_DMA_QMAN_LENGTH 4096
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#define HBM_DMA_QMAN_SIZE_IN_BYTES \
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(HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
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#define TPC_QMAN_LENGTH 1024
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#define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
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#define NIC_QMAN_LENGTH 4096
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#define NIC_QMAN_SIZE_IN_BYTES (NIC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
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#define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START
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/* Virtual address space */
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#define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */
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#define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 512GB */
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#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
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VA_HOST_SPACE_START) /* 767TB */
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#define HOST_SPACE_INTERNAL_CB_SZ SZ_2M
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#define HW_CAP_PLL BIT(0)
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#define HW_CAP_HBM BIT(1)
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#define HW_CAP_MMU BIT(2)
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#define HW_CAP_MME BIT(3)
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#define HW_CAP_CPU BIT(4)
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#define HW_CAP_PCI_DMA BIT(5)
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#define HW_CAP_MSI BIT(6)
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#define HW_CAP_CPU_Q BIT(7)
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#define HW_CAP_HBM_DMA BIT(8)
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#define HW_CAP_SRAM_SCRAMBLER BIT(10)
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#define HW_CAP_HBM_SCRAMBLER BIT(11)
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#define HW_CAP_NIC0 BIT(14)
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#define HW_CAP_NIC1 BIT(15)
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#define HW_CAP_NIC2 BIT(16)
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#define HW_CAP_NIC3 BIT(17)
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#define HW_CAP_NIC4 BIT(18)
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#define HW_CAP_NIC5 BIT(19)
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#define HW_CAP_NIC6 BIT(20)
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#define HW_CAP_NIC7 BIT(21)
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#define HW_CAP_NIC8 BIT(22)
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#define HW_CAP_NIC9 BIT(23)
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#define HW_CAP_NIC_MASK GENMASK(23, 14)
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#define HW_CAP_NIC_SHIFT 14
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#define HW_CAP_TPC0 BIT(24)
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#define HW_CAP_TPC1 BIT(25)
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#define HW_CAP_TPC2 BIT(26)
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#define HW_CAP_TPC3 BIT(27)
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#define HW_CAP_TPC4 BIT(28)
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#define HW_CAP_TPC5 BIT(29)
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#define HW_CAP_TPC6 BIT(30)
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#define HW_CAP_TPC7 BIT(31)
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#define HW_CAP_TPC_MASK GENMASK(31, 24)
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#define HW_CAP_TPC_SHIFT 24
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#define NEXT_SYNC_OBJ_ADDR_INTERVAL \
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(mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 - \
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mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0)
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#define NUM_OF_MME_ENGINES 2
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#define NUM_OF_MME_SUB_ENGINES 2
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#define NUM_OF_TPC_ENGINES 8
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#define NUM_OF_DMA_ENGINES 8
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#define NUM_OF_QUEUES 5
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#define NUM_OF_STREAMS 4
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#define NUM_OF_FENCES 4
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#define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39)
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#define GAUDI_PCI_TO_CPU_ADDR(addr) \
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do { \
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(addr) &= ~GENMASK_ULL(49, 39); \
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(addr) |= BIT_ULL(39); \
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} while (0)
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#define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \
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do { \
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(addr) &= ~GENMASK_ULL(49, 39); \
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(addr) |= (u64) (extension) << 39; \
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} while (0)
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enum gaudi_dma_channels {
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GAUDI_PCI_DMA_1,
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GAUDI_PCI_DMA_2,
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GAUDI_HBM_DMA_1,
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GAUDI_HBM_DMA_2,
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GAUDI_HBM_DMA_3,
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GAUDI_HBM_DMA_4,
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GAUDI_HBM_DMA_5,
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GAUDI_HBM_DMA_6,
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GAUDI_DMA_MAX
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};
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enum gaudi_tpc_mask {
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GAUDI_TPC_MASK_TPC0 = 0x01,
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GAUDI_TPC_MASK_TPC1 = 0x02,
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GAUDI_TPC_MASK_TPC2 = 0x04,
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GAUDI_TPC_MASK_TPC3 = 0x08,
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GAUDI_TPC_MASK_TPC4 = 0x10,
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GAUDI_TPC_MASK_TPC5 = 0x20,
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GAUDI_TPC_MASK_TPC6 = 0x40,
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GAUDI_TPC_MASK_TPC7 = 0x80,
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GAUDI_TPC_MASK_ALL = 0xFF
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};
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enum gaudi_nic_mask {
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GAUDI_NIC_MASK_NIC0 = 0x01,
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GAUDI_NIC_MASK_NIC1 = 0x02,
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GAUDI_NIC_MASK_NIC2 = 0x04,
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GAUDI_NIC_MASK_NIC3 = 0x08,
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GAUDI_NIC_MASK_NIC4 = 0x10,
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GAUDI_NIC_MASK_NIC5 = 0x20,
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GAUDI_NIC_MASK_NIC6 = 0x40,
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GAUDI_NIC_MASK_NIC7 = 0x80,
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GAUDI_NIC_MASK_NIC8 = 0x100,
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GAUDI_NIC_MASK_NIC9 = 0x200,
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GAUDI_NIC_MASK_ALL = 0x3FF
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};
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/*
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* struct gaudi_hw_sob_group - H/W SOB group info.
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* @hdev: habanalabs device structure.
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* @kref: refcount of this SOB group. group will reset once refcount is zero.
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* @base_sob_id: base sob id of this SOB group.
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* @queue_id: id of the queue that waits on this sob group
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*/
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struct gaudi_hw_sob_group {
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struct hl_device *hdev;
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struct kref kref;
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u32 base_sob_id;
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u32 queue_id;
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};
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#define NUM_SOB_GROUPS (HL_RSVD_SOBS * QMAN_STREAMS)
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/**
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* struct gaudi_collective_properties -
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* holds all SOB groups and queues info reserved for the collective
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* @hw_sob_group: H/W SOB groups.
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* @next_sob_group_val: the next value to use for the currently used SOB group.
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* @curr_sob_group_idx: the index of the currently used SOB group.
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* @mstr_sob_mask: pre-defined masks for collective master monitors
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*/
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struct gaudi_collective_properties {
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struct gaudi_hw_sob_group hw_sob_group[NUM_SOB_GROUPS];
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u16 next_sob_group_val[QMAN_STREAMS];
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u8 curr_sob_group_idx[QMAN_STREAMS];
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u8 mstr_sob_mask[HL_COLLECTIVE_RSVD_MSTR_MONS];
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};
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/**
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* struct gaudi_internal_qman_info - Internal QMAN information.
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* @pq_kernel_addr: Kernel address of the PQ memory area in the host.
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* @pq_dma_addr: DMA address of the PQ memory area in the host.
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* @pq_size: Size of allocated host memory for PQ.
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*/
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struct gaudi_internal_qman_info {
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void *pq_kernel_addr;
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dma_addr_t pq_dma_addr;
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size_t pq_size;
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};
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/**
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* struct gaudi_device - ASIC specific manage structure.
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||
|
|
* @cpucp_info_get: get information on device from CPU-CP
|
||
|
|
* @hw_queues_lock: protects the H/W queues from concurrent access.
|
||
|
|
* @internal_qmans: Internal QMANs information. The array size is larger than
|
||
|
|
* the actual number of internal queues because they are not in
|
||
|
|
* consecutive order.
|
||
|
|
* @hbm_bar_cur_addr: current address of HBM PCI bar.
|
||
|
|
* @events: array that holds all event id's
|
||
|
|
* @events_stat: array that holds histogram of all received events.
|
||
|
|
* @events_stat_aggregate: same as events_stat but doesn't get cleared on reset
|
||
|
|
* @hw_cap_initialized: This field contains a bit per H/W engine. When that
|
||
|
|
* engine is initialized, that bit is set by the driver to
|
||
|
|
* signal we can use this engine in later code paths.
|
||
|
|
* Each bit is cleared upon reset of its corresponding H/W
|
||
|
|
* engine.
|
||
|
|
* @multi_msi_mode: whether we are working in multi MSI single MSI mode.
|
||
|
|
* Multi MSI is possible only with IOMMU enabled.
|
||
|
|
* @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an
|
||
|
|
* 8-bit value so use u8.
|
||
|
|
*/
|
||
|
|
struct gaudi_device {
|
||
|
|
int (*cpucp_info_get)(struct hl_device *hdev);
|
||
|
|
|
||
|
|
/* TODO: remove hw_queues_lock after moving to scheduler code */
|
||
|
|
spinlock_t hw_queues_lock;
|
||
|
|
|
||
|
|
struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE];
|
||
|
|
|
||
|
|
struct gaudi_collective_properties collective_props;
|
||
|
|
|
||
|
|
u64 hbm_bar_cur_addr;
|
||
|
|
|
||
|
|
u32 events[GAUDI_EVENT_SIZE];
|
||
|
|
u32 events_stat[GAUDI_EVENT_SIZE];
|
||
|
|
u32 events_stat_aggregate[GAUDI_EVENT_SIZE];
|
||
|
|
u32 hw_cap_initialized;
|
||
|
|
u8 multi_msi_mode;
|
||
|
|
u8 mmu_cache_inv_pi;
|
||
|
|
};
|
||
|
|
|
||
|
|
void gaudi_init_security(struct hl_device *hdev);
|
||
|
|
void gaudi_ack_protection_bits_errors(struct hl_device *hdev);
|
||
|
|
int gaudi_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
|
||
|
|
void gaudi_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
|
||
|
|
void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid);
|
||
|
|
|
||
|
|
#endif /* GAUDIP_H_ */
|